verilog中,产生毛刺是一个常见的现象。目前发现的一种毛刺产生的原因,是由于上升沿与下降沿的与操作,使得系统产生了毛刺,如下:
reg [3:0]acount
reg sclk;
always(posedge clk)
if(!rst_n )
begin
acount <= 4'b0;
sclk <= 1'b0;
end
if(acount == 4'd10)
begin
sclk <= ~sclk;
acount <= 4'b0;
end
else
acount <= acount + 1'b1;
reg flag;
reg [3:0]acount1;
always(posege sclk or negedfe rst)
if(!rst)
begin
flag <= 1'b0;
acount1 <= 4'b0;
end
else if(acount1 < 6)
begin
flag <= 1'b1;
acount1 <= acount1 + 1'b1;
end
else
flag <= 1'b0;