uvm_config_db::set一次能get多次吗？

以int型变量为例 

module test();
    
    import uvm_pkg::*;
    `include "uvm_macros.svh"

    
    class comp1 extends uvm_component;
        `uvm_component_utils(comp1)
        int t;
        function new(string name ="comp1",uvm_component parent);
            super.new(name,parent);
        endfunction 

        task get_config();
            uvm_config_db#(int)::get(this,"","t",t);
            $display("@%0t get the 1st,t = %0d",$time,t);
            #10;
            if(!uvm_config_db#(int)::get(this,"","t",t)) begin
                $display("@%0t Can't get 2nd!",$time);
                t = 99;
            end 
            else 
                $display("@%0t get the 2nd,t = %0d",$time,t);

        endtask
    endclass 

    class comp2 extends uvm_component;
        `uvm_component_utils(comp2)
        int t;
        function new(string name ="comp2",uvm_component parent);
            super.new(name,parent);
        endfunction 
    endclass 
    
    class test extends uvm_component;
        `uvm_component_utils(test)
        comp1 c1;
        comp2 c2;
        int t;
        function new(string name = "test",uvm_component parent);
            super.new(name,parent);
            t = 10;
            uvm_config_db #(int)::set(this,"c1","t",t);

            c1 = new("c1",this);
            c2 = new("c2",this);
        endfunction 

        function display;
            $display("\n\nc1.t = %0d",c1.t);
            $display("c2.t = %0d",c2.t);
        endfunction
    endclass 

    initial begin
        test t1;
        t1 = new("t1",null);
        t1.c1.get_config();
        t1.display();
    end 
endmodule

在顶层test 创建c1 和 c2 组件，test中set到c1一次int变量，c1 任务get两次。结果如下：

可以看到c1 get 的两次都成功了。