1.Verilog语法错误
FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition
from which it cannot recover. Process will terminate. For technical support
on this issue, please open a WebCase with this project attached at
http://www.xilinx.com/support.
Time: 5 ns Iteration: 2 Process:
/JPEGLS_Compress_tb/JPEGLS_Compress_tb/Pixel_Rebuild_inst/Always376_55
错误原因:在generate for中的几个并行电路,always@(*)块中的组合逻辑,使用过程赋值语句,将变量多次赋值给相同的寄存器,如下:
genvar i;
generate
for(i=0; i<`MaxNear; i=i+1) begin:Pr_Loop
always@(*)
begin
PX[i] = (Qs_sign_d1[i])?(Px_pre_d3[i] - C_pre[i] ):((Px_pre_d3[i] + C_pre[i] ));
if( PX[i][16] == 1'b1) PX[i] =0;
else if(PX[i] > `MaxValue) PX[i] = `MaxValue;
else PX[i] = PX[i];
end
......
end
endgenerate
添加中间寄存器,该为:
genvar i;
generate
for(i=0; i<`MaxNear; i=i+1) begin:Pr_Loop
always@(*)
begin
PX_temp[i] = (Qs_sign_d1[i])?(Px_pre_d3[i] - C_pre[i] ):((Px_pre_d3[i] + C_pre[i] ));
if( PX_temp[i][16] == 1'b1) PX[i] =0;
else if(PX_temp[i] > `MaxValue) PX[i] = `MaxValue;
else PX[i] = PX_temp[i];
end
......
end
endgenerate
2. vivado 仿真时闪退
vivado在进行仿真时,尤其是仿真波形信号过多时,会产生大量的临时文件。默认存储在C盘,具体位置:
C:\users\Administrator\AppData\Local\Temp
当磁盘容量不足时,导致vivado闪退。
解决办法:
通过修改用户的环境变量,可以将系统产生的TEMP文件存放在较大的盘上。如下: