hdlbits_Exams/ece241_2014_q5b

https://hdlbits.01xz.net/wiki/Exams/ece241_2014_q5b

module top_module (
    input clk,
    input areset,
    input x,
    output z
); 
	parameter A=0,B=1;
    reg state, next;
    
    always @(*)
        begin
            case(state)
                A: next = x?B:A;
                B: next = x?B:B;
            endcase
        end
    
    always@(posedge clk or posedge areset)
        begin
            if (areset)
                state <= A;
            else
                state <= next;
        end
    
    assign z=(state==B & x==0)|(state==A & x==1);
endmodule