序列检测:5个1,dsic输出1;6个1,flag输出1;7个或以上,err输出1。
这题比较简单,直接附代码。
module top_module(
input clk,
input reset, // Synchronous reset
input in,
output disc,
output flag,
output err);
localparam none=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6,DISC=7,FLAG=8,error=9;
reg[3:0] state,next;
always@(*)
begin
case(state)
none:next=in?s1:none;
s1:next=in?s2:none;
s2:next=in?s3:none;
s3:next=in?s4:none;
s4:next=in?s5:none;
s5:next=in?s6:DISC;
s6:next=in?error:FLAG;
DISC:next=in?s1:none;
FLAG:next=in?s1:none;
error:next=in?error:none;
endcase
end
always@(posedge clk)
begin
if(reset)
state<=none;
else
state<=next;
end
assign disc = (state==DISC);
assign flag = (state==FLAG);
assign err = (state==error);
endmodule