HDLbits--Fsm hdlc

module top_module(
input clk,
input reset, // Synchronous reset
input in,
output disc,
output flag,
output err);

parameter [3:0] start=0, s1=1, s2=2, s3=3, s4=4, s5=5, s6=6, F=7, E=8, D=9;
reg [3:0]state, next;

always@(posedge clk)begin
    if(reset)
        state <= start;
    else
        state <= next;
end

always@(*)begin
    case(state)
        start: next = in ? s1 : start;
        s1: next = in ? s2 : start;
        s2: next = in ? s3 : start;
        s3: next = in ? s4 : start;
        s4: next = in ? s5 : start;
        s5: next = in ? s6 : D;
        s6: next = in ? E : F;
        D: next = s1;
        F: next = in ? s1 : start;
        E: next = in ? E : start;
        default: next = start;
    endcase
end

always@(*)begin
    disc = (state==D);
    flag = (state==F);
    err  = (state==E);
end

endmodule