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文章目录
前言
在前面的练习中,我们使用了简单的逻辑门和几个逻辑门的组合。这些电路是组合电路的例子。组合意味着电路的输出是其输入的函数(在数学意义上)。这意味着对于任何给定的输入值,只有一个可能的输出值。因此,描述组合函数行为的一种方法是显式列出输入的每个可能值的输出。这是真值表。
对于一个有N个输入的布尔函数,有2^N
种可能的输入组合。真值表的每一行列出一个输入组合,所以总有(2^N)行。输出列显示了每个输入值的输出。上面的真值表适用于三输入一输出的函数。对于8种可能的输入组合,每一种都有8行,还有一个输出列。有四种输入组合,其中输出为1,还有四种输出为0。
一、Basic Gates
1.wire
Practice:Implement the following circuit:
翻译:实现如图的电路
Solution(不唯一,仅供参考):
module top_module (
input in,
output out);
assign out = in;
endmodule
2.GND
Practice:Implement the following circuit:
翻译:实现以下电路
Solution(不唯一,仅供参考):
module top_module (
output out);
assign out = 1'b0;
endmodule
3.NOR
Practice:Implement the following circuit:
翻译:实现以下电路
Solution(不唯一,仅供参考):
module top_module (
input in1,
input in2,
output out);
assign out = ~(in1 | in2);
endmodule
4.Another gate
Practice:Implement the following circuit:
翻译:实现以下电路
Solution(不唯一,仅供参考):
module top_module (
input in1,
input in2,
output out);
assign out = in1&(~in2);
endmodule
5.Two gates
Practice:Implement the following circuit:
翻译:实现以下电路
Solution(不唯一,仅供参考):
module top_module (
input in1,
input in2,
input in3,
output out);
assign out =(~(in1^in2))^in3;
endmodule
6.More logic gates
Practice:building several logic gates at the same time. Build a combinational circuit with two inputs, a and b.
翻译:构建几个逻辑门
Solution(不唯一,仅供参考):
module top_module(
input a, b,
output out_and,
output out_or,
output out_xor,
output out_nand,
output out_nor,
output out_xnor,
output out_anotb
);
assign out_and = a&b;
assign out_or = a|b;
assign out_xor = a^b;
assign out_nand = ~(a&b);
assign out_nor = ~(a|b);
assign out_xnor = ~(a^b);
assign out_anotb = a&(~b);
endmodule
Timing Diagram
7.7420 chip
Practice:Create a module with the same functionality as the 7420 chip. It has 8 inputs and 2 outputs.
翻译:创建一个功能与7420芯片相同的模块。它有8个输入2个输出,如下图。
Solution(不唯一,仅供参考):
module top_module (
input p1a, p1b, p1c, p1d,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y );
assign p1y = ~(p1a&p1b&p1c&p1d);
assign p2y = ~(p2a&p2b&p2c&p2d);
endmodule
Timing Diagram
8.Truth tables
Practice:Create a combinational circuit that implements the above truth table.
翻译:创建一个实现上述真值表的组合电路。
Solution(不唯一,仅供参考):
使用generate语句(具体使用看总结)
module top_module(
input x3,
input x2,
input x1, // three inputs
output f // one output
);
always @(*)begin
case({x3,x2,x1})
3'b000: f = 0;
3'b001: f = 0;
3'b010: f = 1;
3'b011: f = 1;
3'b100: f = 0;
3'b101: f = 1;
3'b110: f = 0;
3'b111: f = 1;
endcase
end
endmodule
Timing Diagram
9.Two-bit equality
Practice:Create a circuit that has two 2-bit inputs A[1:0] and B[1:0], and produces an output z. The value of z should be 1 if A = B, otherwise z should be 0.
翻译:创建一个电路,有两个2位输入a[1:0]和B[1:0],并产生一个输出z。如果a = B, z的值应为1,否则z应为0。
Solution(不唯一,仅供参考):
module top_module ( input [1:0] A, input [1:0] B, output z );
always @(*)begin
if(A==B)begin
z = 1;
end
else begin
z = 0;
end
end
endmodule
10.Simple circuit A
Practice:Module A is supposed to implement the function z = (x^y) & x. Implement this module.
翻译:模块A应该实现函数z = (x^y) & x。实现这个模块。
Solution(不唯一,仅供参考):
module top_module (input x, input y, output z);
assign z = (x^y)&x;
endmodule
11.Simple circuit B
Practice:Circuit B can be described by the following simulation waveform,Implement this circuit.
翻译:构建以下电路,电路B可以用如下仿真波形来描述。
提示:从波形图可以看出z=~(x^y)
Solution(不唯一,仅供参考):
module top_module ( input x, input y, output z );
assign z = ~(x^y);
endmodule
Timing Diagram
12.Combine circuits A and B
Practice:Implement this circuit…
翻译:实现以下电路。
Problem 52 Simple circuit A:z = (x ^ y) & x
Problem 53 Simple circuit B:z = x ^~ y
Solution(不唯一,仅供参考):
module top_module (input x, input y, output z);
wire z_A1,z_A2,z_B1,z_B2;
assign z_A1 = (x ^ y) & x;
assign z_A2 = (x ^ y) & x;
assign z_B1 = x ^~ y;
assign z_B2 = x ^~ y;
assign z = (z_A1 | z_B1)^(z_A2&z_B2);
endmodule
13.Ring or vibrate
Practice:Suppose you are designing a circuit to control a cellphone’s ringer and vibration motor. Whenever the phone needs to ring from an incoming call (input ring), your circuit must either turn on the ringer (output ringer = 1) or the motor (output motor = 1), but not both. If the phone is in vibrate mode (input vibrate_mode = 1), turn on the motor. Otherwise, turn on the ringer.
翻译:假设你正在设计一个控制手机铃声和振动电机的电路。当手机来电时(input ring),电路必须把震动( output motor = 1 )或响铃( output ringer = 1 )打开,但不能同时打开。当手机处于震动模式时( input vibrate = 1 ),则打开震动( output motor = 1 ),否则打开响铃。请仅使用 assign 语句来实现该组合电路。
Solution(不唯一,仅供参考):
module top_module (
input ring,
input vibrate_mode,
output ringer, // Make sound
output motor // Vibrate
);
assign motor = ring&vibrate_mode;
assign ringer = ring&(~vibrate_mode);
endmodule
Timing Diagram
14.Thermostat
Practice:The thermostat can be in one of two modes: heating (mode = 1) and cooling (mode = 0). In heating mode, turn the heater on when it is too cold (too_cold = 1) but do not use the air conditioner. In cooling mode, turn the air conditioner on when it is too hot (too_hot = 1), but do not turn on the heater. When the heater or air conditioner are on, also turn on the fan to circulate the air. In addition, the user can also request the fan to turn on (fan_on = 1), even if the heater and air conditioner are off.Try to use only assign statements, to see whether you can translate a problem description into a collection of logic gates.
翻译:一个冷/热恒温控制器可以同时在冬季和夏季对温度进行调节。设计一个电路,根据需要打开和关闭加热器、空调和鼓风机风扇。恒温器可以处于两种模式之一:制热(mode = 1)和制冷(mode = 0)。在制热模式下,当温度过低时(too_cold = 1),打开加热器,但不要使用空调。在制冷模式下,当温度过高(too_hot = 1)打开空调,但不要打开加热器。当加热器或空调打开时,也打开风扇使空气循环。此外,即使加热器和空调关闭,用户也可以请求将风扇打开(fan_on = 1)。尝试仅使用assign语句来设计该电路。
Solution(不唯一,仅供参考):
module top_module (
input too_cold,
input too_hot,
input mode,
input fan_on,
output heater,
output aircon,
output fan
);
assign heater = mode&too_cold;
assign aircon = (~mode)&too_hot;
assign fan = (mode&too_cold) | ((~mode)&too_hot) | fan_on;
endmodule
错误:
assign fan = too_cold | too_hot | (fan_on&(~too_cold)&(~too_hot));
未将mode信号考虑到
改正:
assign fan = (mode&too_cold) | ((~mode)&too_hot) | fan_on;
Timing Diagram
15.3-bit population count
Practice:A “population count” circuit counts the number of '1’s in an input vector. Build a population count circuit for a 3-bit input vector.
翻译:计算输入信号in中“1”的数量
Solution(不唯一,仅供参考):
module top_module(
input [2:0] in,
output [1:0] out );
always @(*) begin
out = 0;
for(int i=0;i<3;i++)begin
out = out+in[i];
end
end
endmodule
Timing Diagram
16.Gates and vectors
Practice:You are given a four-bit input vector in[3:0]. We want to know some relationships between each bit and its neighbour:
翻译:给你一个4位输入向量[3:0]。我们想知道每个比特和它的邻居之间的一些关系:
out_both: 输入的每一个 bit 均需要检测该 bit 位与其左侧(即高比特位)是否全为 ‘ 1 ’ 。
示例: out_both[2] 应检测 in[2] 与 in[3] 是否均为 ‘ 1 ’ 。in[3] 为输入的最高位,无需out_both[3]。
out_any: 输入的每一个 bit 均需要检测该 bit 位与其右侧(即低比特位)两者其中一个是否为 ‘ 1 ’ 。
示例: out_any[2] 应检测 in[2] 与 in[1] 两者其中一个为 ‘ 1 ’ 。in[0] 为输入的最低位,无需 out_any[0]。
out_different: 输入的每一个 bit 均需要检测该 bit 位与其左侧(即高比特位)两者是否不同。
示例: out_different[2] 应检测 in[2] 与 in[3] 两者是否不同 ,将输入变成一个环,所以 in[3] 的左侧为 in[0]。
Solution(不唯一,仅供参考):
module top_module(
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different );
assign out_both[2] = in[2]&in[3];
assign out_both[1] = in[1]&in[2];
assign out_both[0] = in[0]&in[1];
assign out_any[3] = in[3] | in[2];
assign out_any[2] = in[2] | in[1];
assign out_any[1] = in[1] | in[0];
assign out_different[3] = (in[3]==in[0])?0:1;
assign out_different[2] = (in[2]==in[3])?0:1;
assign out_different[1] = (in[1]==in[2])?0:1;
assign out_different[0] = (in[0]==in[1])?0:1;
endmodule
上述方法比较直接,改进:
assign out_both = in[2:0] & in[3:1];
assign out_any = in[3:1] | in[2:0];
assign out_different = in ^ {in[0], in[3:1]};
大佬方法:
module top_module(
input [3:0] in,
output reg [2:0] out_both,
output reg [3:1] out_any,
output reg [3:0] out_different );
integer i;
always @(*) begin
for (i = 0; i<=3; i=i+1) begin
if(i != 3) out_both[i] = in[i] & in[i+1];
if(i != 0) out_any[i] = in[i] | in[i-1];
if(i != 3) out_different[i] = in[i] ^ in[i+1];
end
out_different[3] = in[3] ^ in[0];
end
endmodule
Timing Diagram
17.Even longer vecrots
Practice:You are given a 100-bit input vector in[99:0]. We want to know some relationships between each bit and its neighbour:
翻译:与上题类似,将4bits改为100bits。
Solution(不唯一,仅供参考):
module top_module(
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different );
assign out_both[2] = in[2]&in[3];
assign out_both[1] = in[1]&in[2];
assign out_both[0] = in[0]&in[1];
assign out_any[3] = in[3] | in[2];
assign out_any[2] = in[2] | in[1];
assign out_any[1] = in[1] | in[0];
assign out_different[3] = (in[3]==in[0])?0:1;
assign out_different[2] = (in[2]==in[3])?0:1;
assign out_different[1] = (in[1]==in[2])?0:1;
assign out_different[0] = (in[0]==in[1])?0:1;
endmodule
上述方法比较直接,改进:
assign out_both = in[2:0] & in[3:1];
assign out_any = in[3:1] | in[2:0];
assign out_different = in ^ {in[0], in[3:1]};
大佬方法:
module top_module(
input [99:0] in,
output reg [98:0] out_both,
output reg [99:1] out_any,
output reg [99:0] out_different );
always @(*)begin
for(int i=0;i<100;i++)begin
if(i!=99) out_both[i] = in[i]&in[i+1];
if(i!=99) out_any[i+1] = in[i+1] | in[i];
if(i!=99) out_different[i] = in[i]^in[i+1];
end
out_different[99] = in[99]^in[0];
end
endmodule
总结
1、 本章内容比较简单,和之前Basics基本相同,可以当作复习。
继续加油!!!!!