FPGA DEBUG

[Place 30-602] IO port 'clk' is driving multiple buffers. This will lead to unplaceable/unroutable situation.
The buffers connected are:
    m_u2/inst/clkin1_ibuf {IBUF}
    m_u1/inst/clkin1_ibuf {IBUF}

[Place 30-99] Placer failed with error: 'IO Clock Placer stopped due to earlier errors. Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
出现类似的错误表示的是，一个时钟接入了两个锁相环中，这是在fpga中不允许的，如果是你时钟不够用了的话，可以修改一下两个锁相环的位置让其形成串联，通过一个锁相环之后，将输出信号再接入另一个锁相环去生成其他时钟即可！

特别注意的一点是：有的IP核（DDR MIG）会自带锁相环，当你把时钟接进去它会先经过锁相环，在操作IP核，所以遇到这种的同上一样的操作就可以避免。