vivado IODELAY_GROUP

IODELAY_GROUP将IDELAYCTRL单元格及其关联的IDELAY和
ODELAY细胞允许正确放置和复制。
如果使用IODELAY_GROUP为IDELAYCTRL分配组名，还需要
使用相同的IODELAY_group属性将IDELAY或ODELAY单元格与组相关联。
重要提示：虽然IODELAY_GROUP可以包含多个单元格，但一个单元格只能分配给一个
碘组。
以下示例使用set_property对所有IDELAY/ODELAY元素进行分组
与特定的IDELAYCTRL相关联。

set_property IODELAY_GROUP IO_DLY1 [get_cells MY_IDELAYCTRL_inst]

set_property IODELAY_GROUP IO_DLY1 [get_cells MY_IDELAY_inst]

set_property IODELAY_GROUP IO_DLY1 [get_cells MY_ODELAY_inst]

IODELAY_GROUP和HIODELAY_GROUP之间的区别
IODELAY_GROUP可以跨不同层次结构对元素进行分组，而
HIODELAY_GROUP名称在每个层次结构中都是唯一的。使用IODELAY_GROUP进行分组
将来自不同层次结构的I/O延迟组件合并到一个组中。
HIODELAY_GROUP将I/O延迟组件分组到同一层次模块下。

Syntax

Verilog Syntax

Place the Verilog attribute immediately before the instantiation of an IDELAY, ODELAY, or

IDELAYCTRL.

(* IODELAY_GROUP = "value" *)

Verilog Syntax Example

// Specifies a group name of DDR_INTERFACE to an instantiated IDELAYCTRL

// IDELAYCTRL: IDELAYE2/ODELAYE2 Tap Delay Value Control

// Virtex-7

// Xilinx HDL Language Template, version 2014.1

// Specifies DDR_INTERFACE group name for IDELAYs/ODELAYs and IDELAYCTRL

(* IODELAY_GROUP = “DDR_INTERFACE” *)

IDELAYCTRL DDR_IDELAYCTRL_inst (

.RDY(), // 1-bit output: Ready output

.REFCLK(REFCLK), // 1-bit input: Reference clock input

.RST(1’b0) // 1-bit input: Active-High reset input

);

// End of DDR_IDELAYCTRL_inst instantiation

VHDL Syntax

Declare the VHDL attribute as follows:

attribute IODELAY_GROUP : string;

For an instantiated instance, specify the VHDL attribute as follows:

attribute IODELAY_GROUP of instance_name : label is "group_name";

Where

• instance_name is the instance name of an instantiated IDELAY, ODELAY, or

IDELAYCTRL.

VHDL Syntax Example

// Specifies a group name of DDR_INTERFACE to an instantiated IDELAYCTRL

attribute IODELAY_GROUP : STRING;

attribute IODELAY_GROUP of DDR_IDELAYCTRL_inst: label is "DDR_INTERFACE";

begin

-- IDELAYCTRL: IDELAYE2/ODELAYE2 Tap Delay Value Control

-- Virtex-7

-- Xilinx HDL Language Template, version 2014.1

DDR_IDELAYCTRL_inst : IDELAYCTRL

port map (

RDY => open, -- 1-bit output: Ready output

REFCLK => REFCLK, -- 1-bit input: Reference clock input

RST => ‘0’ -- 1-bit input: Active-High reset input

);

-- End of DDR_IDELAYCTRL_inst instantiation

XDC Syntax

set_property IODELAY_GROUP group_name [get_cells instance_name]

Where

• group_name is a user-specified name for the IODELAY_GROUP.

• instance_name is the instance name of an IDELAY, ODELAY, or IDELAYCTRL.

XDC Syntax Example

# Specifies a group name of DDR_INTERFACE to an instantiated IDELAYCTRL

set_property IODELAY_GROUP DDR_INTERFACE [get_cells DDR_IDELAYCTRL_inst]