[DRC 23-20] Rule violation (PLIDC-7) IDELAYCTRL DRC Checks - Design has more than one unlocked and ungrouped IDELAYCTRL instances. Please instantiate a delay controller (or use an existing one if delay values allow so) and apply appropriate IODELAY_GROUP or LOC constraints on the delay instances, or instantiate only one delay controller for the design without any IODELAY_GROUP or LOC constraints. The instances involved are:
U0_IDELAYCTRL
U1_IDELAYCTRL
VIVADO在生成bit文件时,会报错(PLIDC-7) ,翻译的意思是:
[DRC 23-20]违反规则(PLDC-7)IDELAYCTRL DRC检查-Design有多个未锁定和未分组的IDELAYCTRL实例。请实例化一个延迟控制器(或在延迟值允许的情况下使用一个现有控制器),并对延迟实例应用适当的IODELAY_GROUP或LOC约束,或为设计仅实例化一个没有任何IODELAY-GROUP或LOC约束的延迟控制器。
解决办法:是因为添加的某个工程没有历化,删除或者历化这个文件即可解决,注意删除的话要把文件所在位置的文件同时删除掉。