Vivado ILA调试的没有波形的小问题

最新推荐文章于 2025-06-17 10:43:04 发布

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最新推荐文章于 2025-06-17 10:43:04 发布

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分类专栏：调试小问题

本文链接：https://blog.csdn.net/christne1225i/article/details/53395802

在Vivado 2015.1版本中，通过标记Netlist信号和设置Synthesis Debug后，发现调试探针未显示任何内容，产生警告提示缺少自由运行时钟。原因是调试默认依赖PS的FCLK，而该时钟在PS启动前不存在。解决方案是在Xilinx SDK中设置程序断点，先运行程序，然后在Open Hardware模式下查看，即可看到波形。

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WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
WARNING: [Labtools 27-1974] Mismatch between the design programmed into the device xc7z010_1 and the probes file E:/Xilinx/example/dma_sg_m/dma_sg_m.runs/impl_1/debug_nets.ltx.
The device design has 0 ILA core(s) and 0 VIO core(s). The probes file has 1 ILA core(s) and 0 VIO core(s).
Resolution:
1. Reprogram device with the correct programming file and associated probes file OR

2. Goto device properties and associate the correct probes f