module Select(
input wire a,
input wire b,
input wire c,
input wire d,
output reg y
);
reg [2:0] sum;//用来计算和
always @(*) begin //************
sum<=a*2+b+c+d;
if (sum>=3'h3) begin
y<=1'b1;
end else begin
y<=1'b0;
end
end
endmodule
接下来是激励程序:
module Select_tb;
reg a,b,c,d;
wire y;
Select ut(a,b,c,d,y);
initial
begin
a=0;b=0;c=0;d=0;#100;
a=0;b=0;c=0;d=1;#100;
a=0;b=0;c=1;d=0;#100;
a=0;b=0;c=1;d=1;#100;
a=0;b=1;c=0;d=0;#100;
a=0;b=1;c=0;d=1;#100;
a=0;b=1;c=1;d=0;#100;
a=0;b=1;c=1;d=1;#100;
a=1;b=0;c=0;d=0;#100;
a=1;b=0;c=0;d=1;#100;
a=1;b=0;c=1;d=0;#100;
a=1;b=0;c=1;d=1;#100;
a=1;b=1;c=0;d=0;#100;
a=1;b=1;c=0;d=1;#100;
a=1;b=1;c=1;d=0;#100;
a=1;b=1;c=1;d=1;#100;
end
endmodule