DRAM Power down mode

 There are three power down modes for , including IDD2P (precharge power down),
IDD3P (active power down, slow exit), and IDD3P (active power down, fast exit). Precharge
power-down occurs when all banks are idle and is the lowest power state other
than self-refresh mode (IDD6). If power-down occurs when there is a row active in any
bank, the mode is referred to as active power-down. For active power down, fast or slow
exit is determined by the configuration of the mode register (MR12 = 0 for fast or MR12 =
1 for slow). The advantage of the slow exit is less device power consumption.
Entering power-down deactivates the input and output buffers, excluding CK, CK#, ODT,
and CKE. For maximum power savings, the DLL generally is frozen during precharge
power-down.
Exiting active power-down requires the device to be at the same voltage and frequency
as when it entered power-down. Exiting precharge power-down requires the device to
be at the same voltage as when it entered power-down; however, the clock frequency is
allowed to change as specified within Micron data sheets.
Maximum power-down duration is governed by the refresh requirements of the device.
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The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as sixteen-banks, 4 bank group with 4 banks for each bank group for x4/x8 and eight-banks, 2 bank group with 4 banks for each bankgroup for x16 DRAM. The DDR4 SDRAM uses a 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR4 SDRAM consists of a single 8n-bit wide, four clock data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write operation to the DDR4 SDRAM are burst oriented, start at a selected location, and continue for a burst length of eight or a ‘chopped’ burst of four in a programmed sequence. Operation begins with the registration of an ACTIVATE Command, which is then followed by a Read or Write command. The address bits registered coincident with the ACTIVATE Command are used to select the bank and row to be activated (BG0-BG1 in x4/8 and BG0 in x16 select the bankgroup; BA0-BA1 select the bank; A0-A17 select the row; refer to “DDR4 SDRAM Addressing” on datasheet). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst operation, determine if the auto precharge command is to be issued (via A10), and select BC4 or BL8 mode ‘on the fly’ (via A12) if enabled in the mode register. Prior to normal operation, the DDR4 SDRAM must be powered up and initialized in a predefined manner. The following sections provide detailed information covering device reset and initialization, register definition, command descriptions, and device operation.
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