一、说明
1、本文主要是验证verilog和C混合编程的功能,即同时使用verilog和C语言来操作双端ram;
2、本文是在nios系统中建立的双端ram,而非在verilog编程下例化的双端ram;
二、本文参考链接
https://blog.csdn.net/programmer_guan/article/details/102720059
三、过程
1、在nios中添加双端ram
2、双端ram的rtl视图
3、verilog操作双端ram
/*-------------------Dual_Port RAM测试代码---------------------------------*/
/********************************************************************/
wire [ 4:0] read_addr;
reg [31:0] read_data;
always @(posedge clk_100m or negedge rst_n)
begin
if (!rst_n)
begin // reset
writedata <= 32'h256;
address <= 5'h0;
end
else if (writedata == 32'hffff_ffff)
begin
writedata <= 32'h0;
address <= 5'h0;
end
else if (write_read) //write_read写使能信号有效时数据跳变
begin
writedata <= writedata + 1'b1;
address <= address + 5'h1;
end
else if (!write_read)
begin
case(read_addr)
5'h03: begin address <= read_addr; read_data <= readdata;end
endcase
end
end
assign read_addr = 5'h03;
assign write_read = (writedata < (32'h256+32'h20 ));//存满32个32bit的数据后write_read拉低
4、NSBT中操作双端ram
for(i=0;i<32*4;i=i+4)
{
data2[k] = IORD_32DIRECT(DUAL_PORT_RAM_BASE,i);//从地址位置为 DUAL_PORT_RAM_BASE+0 的寄存器中直接读取 32Bit的数据
printf("data_%d=%x\t",k,data2[k]);
k = k+1;
}
IOWR_32DIRECT(DUAL_PORT_RAM_BASE, 12, 32); //往地址位置为 DUAL_PORT_RAM_BASE+8 的寄存器中直接写入 32Bit 的数据
k=0;
for(i=0;i<32*4;i=i+4)
{
data2[k] = IORD_32DIRECT(DUAL_PORT_RAM_BASE,i);//从地址位置为 DUAL_PORT_RAM_BASE+0 的寄存器中直接读取 32Bit的数据
printf("data_%d=%x\t",k,data2[k]);
k = k+1;
}
四、源码工程
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