（2，1，2）卷积码的维特比译码Verilog实现

Verilog代码块

`timescale 1ns / 1ps
module viterbi(
  input  clk,
  input  clk_div2,
  input  rst_n,  //
  input  x,
  output y,
  output c,
  output reg rd,
  output reg ready);  
  reg[13:0]     x_t,x_t1;
  reg[3:0]      cnt;
  reg[2:0]      cnt2;
  reg[13:0]     a_out,a_out1,a1,a2,a3,a4;
  reg[3:0]      c1,c2,c3,c4; 
  reg[6:0]      c_t,c_t1,c_t2,c_t3,c_t4;
  reg[6:0]      c_t5;
   always@(posedge clk)begin
   if(!rst_n)begin
        x_t   <=  0;
    x_t1  <=  0;
    cnt   <=  0;
  end
   else begin
   if(cnt == 4'b1101)
        cnt   <= 4'b0000;        
   else
        cnt  <= cnt + 1;
    x_t1 <= {x,x_t1[13:1]};
         if(cnt == 4'b0000)begin
              x_t <= x_t1;
             end
          else
              x_t <= x_t;
   end 
  end
   always@(posedge clk_div2)begin
  if(!rst_n)begin
       cnt2 <= 0;
   a1   <= 0;
   a2   <= 0;
   a3   <= 0;
   a4   <= 0; 
   c1   <= 0;
   c2   <= 0;
   c3   <= 0;
   c4   <= 0;
   c_t1 <= 0;
   c_t2 <= 0;
   c_t3 <= 0;
   c_t4 <= 0;
  end
 else begin
   cnt2 <= cnt2  + 1;
     case(cnt2)
       3'b000: begin
         a1[1:0]  <= 2'b00;
         a2[1:0]  <= 2'b00;
         a3[1:0]  <= 2'b11;
         a4[1:0]  <= 2'b11;
         a1[13:2] <= 0;
         a2[13:2] <= 0;
         a3[13:2] <= 0;
         a4[13:2] <= 0;
         c1  <= 0;
         c2  <= 0;
         c3  <= 0;
         c4  <= 0;    
         c_t1[6]  <= 0;
         c_t2[6]  <= 0;
         c_t3[6]  <= 1;
         c_t4[6]  <= 1;
      end
     3'b001 : begin
          a1[3:2]  <= 2'b00;
          a2[3:2]  <= 2'b11;
          a3[3:2]  <= 2'b01;
          a4[3:2]  <= 2'b10;     
       c1  <= {
  3'b000,0^x_t[0]} + {
  3'b000,0^x_t[1]} +
                   {
  3'b000,0^x_t[2]} + {
  3'b000,0^x_t[3]};
       c2  <= {
  3'b000,0^x_t[0]} + {
  3'b000,0^x_t[1]} +
                   {
  3'b000,1^x_t[2]} + {
  3'b000,1^x_t[3]};
       c3  <= {
  3'b000,1^x_t[0]} + {
  3'b000,1^x_t[1]} +
                   {
  3'b000,1^x_t[2]} + {
  3'b000,0^x_t[3]};
       c4  <= {
  3'b000,1^x_t[0]} + {
  3'b000,1^x_t[1]} +
                   {
  3'b000,0^x_t[2]} + {
  3'b000,1^x_t[3]};   
       c_t1[5] <= 0;
       c_t2[5] <= 1;
       c_t3[5] <= 0;
       c_t4[5] <= 1;
    end    
     3'b010 : begin
         //  a = 2'b00
     if(c1 + {
  3'b000,0^x_t[5]} + {
  3'b000,0^x_t[4]} >
         c3 + {
  3'b000,1^x_t[5]} + {
  3'b000,1^x_t[4]})
      begin
       c1 <= c3 + {
  3'b000,1^x_t[5]} + {
  3'b000,1^x_t[4]};
       a1[3:0]    <= a3[3:0];
       a1[5:4]    <= 2'b11;
       c_t1[4]     <= 1'b0;
       c_t1[6:5]  <= c_t3[6:5];
      end
     else begin 
       c1 <= c1 + {
  3'b000,0^x_t[5]} + {
  3'b000,0^x_t[4]};
       a1[3: