1. 题目
- 奇校验码:
奇校验码在数据发送前,「检查」1的个数,「奇数」个1就在头部填充0,「偶数」个1就在头部填充1,使数据整体保持奇数个1;
接收数据时,重新检查1的个数:
「奇数」个则判定数据正常,去掉头部的填充符;
「偶数」个则判定数据出错,重新发送数据帧。
- 偶校验码:
偶校验码在数据发送前,也会「检查」1的个数,「偶数」个1就在头部填充0,「奇数」个1就在头部填充1,使数据整体保持偶数个1;
接收数据时,重新检查1的个数:
「偶数」个1则判定数据正常,去掉头部的填充符;
「奇数」个1则判定数据异常,重新发送数据帧。
- 「检查」1的个数:
对输入数据按位异或操作,即is_odd = ^bus。
is_odd = 1:表示1的个数为奇数个;
is_odd = 0:表示1的个数为偶数个。
2. RTL代码
观察本题提供的波形图,实现过程较为简单,只需要检测原始数据中“1”的个数即可,不需要添加校验位。
`timescale 1ns/1ns
module odd_sel
(
input wire [31:0] bus,
input wire sel,
output wire check
);
wire is_odd;
assign is_odd = ^bus;//1:the number of "1" is odd;0:the number of "1" is even.
assign check = (sel) ? is_odd : ~is_odd;
endmodule
3. Tb
`timescale 1ns/1ns
`define odd 2'b00
`define even 2'b01
`define random 2'b10
module tb();
reg clk ;
reg rst_n ;
reg [31:0] bus ;
reg sel ;
reg check ;
initial begin
clk = 0;
rst_n = 1;
bus = 32'b0;
sel = 0;
repeat(10)@(posedge clk);
rst_n = 0;
repeat(20)@(posedge clk);
rst_n = 1;
bus_case(bus,0);
sel_case(sel,`odd);
bus_case(bus,1);
sel_case(sel,`even);
bus_case(bus,2);
sel_case(sel,`even);
bus_case(bus,3);
sel_case(sel,`even);
bus_case(bus,4);
sel_case(sel,`odd);
bus_case(bus,5);
sel_case(sel,`odd);
bus_case(bus,6);
sel_case(sel,`odd);
bus_case(bus,7);
sel_case(sel,`even);
bus_case(bus,8);
sel_case(sel,`even);
bus_case(bus,9);
sel_case(sel,`even);
repeat(100)begin
bus_case(bus,10);
sel_case(sel,`random);
end
repeat(20)@(posedge clk);
$finish;
end
//***** clock period is 20ns *****//
always begin
#10 clk = ~clk;
end
//***** generate task *****//
task bus_case;
output [31:0] a;
input [3:0] b;
case(b)
0 : #40 a = 32'd0;
1 : #40 a = 32'd1;
2 : #40 a = 32'd2;
3 : #40 a = 32'd3;
4 : #40 a = 32'd4;
5 : #40 a = 32'd5;
6 : #40 a = 32'd6;
7 : #40 a = 32'd7;
8 : #40 a = 32'd8;
9 : #40 a = 32'd9;
10: #40 a = {$random}%32'hffffffff;
endcase
endtask
task sel_case;
output a;
input [1:0] b;
case(b)
`odd : a = 1'b0;
`even : a = 1'b1;
`random : a = {$random}%2;
endcase
endtask
//***** generate wave file *****//
initial begin
$fsdbDumpfile("tb.fsdb");
$fsdbDumpvars(0,tb);
end
odd_sel U1(
.bus (bus),
.sel (sel),
.check (check)
);
endmodule