GIC 600

1、About GIC 600

A generic interrupt controller, that handles interrupts from peripherals to the cores and between cores.通用的中断控制器，处理来自外设到core的中断，和core之间的中断。

GICD : GIC Distributor.

GITS : GIC Interrupt Translation Service

GICR : GIC Redistributor

SPI : Shared Peripheral Interrupts

PPI : Private Peripheral Interrupts

LPI : Locally specific Peripheral Interrupts

SGI : Software Generated Interrupts

ADB ： AMBA Domain Bridge

2、Feature

The GIC-600 provides register for managing interrupt sources, interrupt behavior, and interrupt routing to one or more cores. 管理中断源，中断行为，分配中断给一个或多个core。

Flexible affinity routing (关联路由，路由选择亲和性)

The GIC-600 uses affinity routing, a hierarchical address-based scheme, to identify connected cores and for routing interrupts to specific cores. 一个分层级的地址策略，来识别连接的core并且分配中断给指定的core。

The ARM architecture defines a register in a core that identifies the logical address of the core in the system. This register, which is known MPIDR(Multiprocessor Affinity Register), has a hierarchical format. Each level of the hierarchy is known as an affinity level, with the highest affinity levels specified first:

--- For an ARMv7 processor, the MPIDR defines three levels of affinity, with an implicit affinity level 3 value of 0.

--- For an ARMv8 processor, the MPIDR defines four levels of affinity.

The affinity of a core is represented by four 8-bit fields using dot-decimal notation, <Aff3>.<Aff2>.<Aff1>.<Aff0>,where Affn is a value for affinity level n. An example of an identification for a specific core would be 0.255.0.15。

The affinity scheme matches the format of the MPIDR_EL1 register in ARMv8-A. System designers must ensure that the ID reported by the core of the MPIDR_EL1 register matches how the core is connected to the interrupt controller.

There can be up to 256 nodes at level 3, with each node able to host 256 child level 2 nodes. Similarly each level 2 node can host 256 level 1 nodes. However, level 1 nodes can only host 16 child level 0 nodes.

aff level 3: 0.x.x.x

aff level 2: 0.0.x.x --> 0.1.x.x --> 0.2.x.x --......--> 0.255.x.x

aff level 1: 0.0.x.x --> 0.0.1.x --...--> 0.0.255.x

                 0.1.x.x --> 0.1.1.x --...--> 0.1.255.x

aff level 0: 0.0.0.0 --> 0.0.0.1 --> 0.0.0.2 --...--> 0.0.0.15

At affinity level 0, there is a Redistributor. Each Redistributor connects to a single core interface. The Redistributor is used to configure SGIs, PPIs, and LPIs.

3、Components

The GIC-600 consists of seven significant components, with an optional structural top level. These components work in combination to create a single architecturally compliant GICv3 implementation within the system.

The GIC-600 consists of the following components:

---- Distributor component 分配器部件

---- GIC Distributor

The Distributor (分配者) is the hub (中心) of all the GIC communications and contains all SPI and LPI functionality for the whole chip, and is responsible for the entire register map, except for the GITS_TRANSLATER register that is hosted in the Interrupt Translation Service (ITS- 中断转换服务) component.

The Distributor also maintains the coherency of the SPI register space in multichip configurations.

---- Redistributor component 再分配器部件

The Redistributor maintains the PPIs and  (SGIs) 软件生成的中断 for a particular core set. A Redistributor can scale from 1-128 cores and is best placed next to the processors they are servicing to reduce wiring to the cores.

The LPI functionality for all cores on a chip is combined into a single cache in the Distributor.

The GIC-600 supports powering down of the Redistributor blocks along with the associated cores if necessary.

---- ITS component (Interrupt Translation Service)

The ITS is responsible for translating message-based interrupt (Message-Signaled Interrupts MSI/MSIx) from PCI Express(PCIe) or other sources. The ITS is also responsible for managing LPIs during core power management. The Gic-600 supports up to 16 ITS blocks per chip.

---- MSI-64 encapsulator component 封装器部件

The MSI-64 Encapsulator is a small block that combines the deviceID required by wires to the GITS_TRANSLATER register into a single memory access.

---- SPI Collator component 整理器，校对机

The GIC-600 supports up to 960 SPIs that are spread across all chips in the system. The SPI Collator enables SPIs to be converted into messages remotely from the Distributor. This enables hierarchical clock gating of the Distributor and the use of other more aggressive low-power states.

---- Wake Request component

The wake request component contains all the architecturally defined wake_request signals for each core on the chip. It is a separate block so it can be positioned remotely from the Distributor, such as next to a system control processor if necessary.

3、Free flowing channel

Free-flowing is a concept whereby a channel is clear to transmit a transaction that arrives at its destination without any non-transient dependencies on other transactions.