Always nolatches

在多个变量赋值前应给予初值，防止产生锁存器

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up  );
    
    always@ (*)
        begin
            left <= 0;down<= 0;right <= 0;up <= 0;
            case(scancode[15:0])
                16'he06b: left <= 1'b1;
                16'he072: down <= 1'b1;
                16'he074: right <= 1'b1;
                16'he075: up <= 1'b1;
                default: begin
                    left <= 0;down<= 0;right <= 0;up <= 0;
                end
            endcase
        end
endmodule