Verilog刷题[hdlbits] ：Always nolatches

题目：Always nolatches

Suppose you’re building a circuit to process scancodes from a PS/2 keyboard for a game. Given the last two bytes of scancodes received, you need to indicate whether one of the arrow keys on the keyboard have been pressed. This involves a fairly simple mapping, which can be implemented as a case statement (or if-elseif) with four cases.

• 假设您正在构建一个电路来处理来自PS/2键盘的游戏扫描码。给定接收到的最后两个字节的扫描码，您需要指示是否按下了键盘上的一个箭头键。这涉及到一个相当简单的映射，它可以被实现为包含四种情况的case语句(或if-elseif)。
  
  Your circuit has one 16-bit input, and four outputs. Build this circuit that recognizes these four scancodes and asserts the correct output.
• 你的电路有一个16位输入和四个输出。构建这个电路来识别这四个扫描码并断言正确的输出。

To avoid creating latches, all outputs must be assigned a value in all possible conditions (See also always_if2). Simply having a default case is not enough. You must assign a value to all four outputs in all four cases and the default case. This can involve a lot of unnecessary typing. One easy way around this is to assign a “default value” to the outputs before the case statement:

• 为了避免产生锁存器，必须在所有可能的条件下为所有输出赋值(参见always_if2)。仅仅有一个默认情况是不够的。您必须为所有四种情况和默认情况下的所有四个输出分配一个值。这可能涉及很多不必要的输入。解决这个问题的一个简单方法是在case语句之前为输出分配一个“默认值”:
  

This style of code ensures the outputs are assigned a value (of 0) in all possible cases unless the case statement overrides the assignment. This also means that a default: case item becomes unnecessary.

• 这种风格的代码确保在所有可能的情况下，输出都被赋值(0)，除非case语句覆盖了赋值。这也意味着没有必要使用default: case项。

Reminder: The logic synthesizer generates a combinational circuit that behaves equivalently to what the code describes. Hardware does not “execute” the lines of code in sequence.

• 提醒:逻辑合成器产生的组合电路的行为等同于代码所描述的。硬件不按顺序“执行”代码行。

个人理解，锁存器具有保持当前状态的功能。在if语句和case语句执行到不包含的情况时，会默认保持原来的状态，此时就生成了锁存器，所以就需要else和default覆盖所有情况。在本题目中，always语句会给所有输出一个默认值，此时就不会出现保持原来状态的情况，就不会生成锁存器了。

// synthesis verilog_input_version verilog_2001
module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up  ); 
    always@(*)
        begin
            left  = 1'b0;
            down  = 1'b0;
            right = 1'b0;
            up    = 1'b0;
            case(scancode)
                16'he06b:	left  = 1'b1;
                16'he072:	down  = 1'b1;
                16'he074:	right = 1'b1;
                16'he075:	up    = 1'b1;
            endcase
        end
endmodule