HDLBits上的Verilog练习

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开始编写吧

门电路

与门

代码如下：

module top_module( 
    input a, 
    input b, 
    output out );
    assign out=a&b;

endmodule

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成功后

或非门

module top_module( 
    input a, 
    input b, 
    output out );
    assign out=!(a|b);
endmodule

同或门

module top_module( 
    input a, 
    input b, 
    output out );
    assign out=!(a^b);

endmodule

组合电路

Mt2015 q4a

module top_module (input x, input y, output z);
    assign z=(x^y) & x;

endmodule

半加器

module top_module( 
    input a, b,
    output cout, sum );
    assign cout=a&b;
    assign sum=a^b;
endmodule

全加器

module top_module( 
    input a, b, cin,
    output cout, sum );
    assign sum=a^b^cin;
    assign cout=(a&b)|(a&cin)|(b&cin);

endmodule

时序电路

D触发器

module top_module (
    input clk,    // Clocks are used in sequential circuits
    input d,
    output reg q );//

    always @(posedge clk)
        q<=d;
    // Use a clocked always block
    //   copy d to q at every positive edge of clk
    //   Clocked always blocks should use non-blocking assignments

endmodule

m2014 q4a

module top_module (
    input d, 
    input ena,
    output q);
    always@(*)begin
        if(ena)begin
            q<=d;
        end
    end
endmodule

DFF (Exams/m2014 q4c)

module top_module (
    input clk,
    input d, 
    input r,   // synchronous reset
    output q);
    always @(posedge clk) begin
        if(r)
            q <= 1'b0;
        else
            q <= d;
    end
endmodule