LIFI光通信——定位系统，源码公布4

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date:    15:33:18 09/28/2010 
// Design Name: 
// Module Name:    dac_inf 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
module power_calu(
                input              sys_clk         ,
                input              rst             , 
                
                input   [13:0]     I_data_in       ,  
                input              I_sync_ok       ,
                 
                input              I_norma_bit_data,
                input   [15:0]     I_data_rate     ,
                input   [15:0]     I_cap_data_cnt  ,      
      
                output  reg [15:0] O_power_out     ,
                input   [7:0]      I_hdm960_gc     ,         
                output  reg [7:0]  O_hdm960_gc     ,
                input              I_crc_check_ok      
                                              
       );
                    
                       
//----------------------------------------------------------------
wire   [15:0]  s_high_power_out;
wire   [15:0]  s_low_power_out ;
reg            crc_ok_d1       ;
reg            crc_ok_d2       ;
wire           crc_ok_rising   ;
reg   [63:0]   delay_shift_reg ;
reg            crc_ok_delay    ; 


//----------------------------------------------------------------

power_calu_one i_power_calu_high(
                                   .sys_clk         (sys_clk         ),
                                   .rst             (rst             ),                 
                                   .I_data_in       (I_data_in       ),  
                                   .I_sync_ok       (I_sync_ok       ),                 
                                   .I_norma_bit_data(I_norma_bit_data),
                                   .I_data_rate     (I_data_rate     ),
                                   .I_cap_data_cnt  (I_cap_data_cnt  ),
                                   .I_high_low_sel  (1'b1            ), //1 calu high power            
                                   .O_power_out     (s_high_power_out)
                                              
       );
       
       
power_calu_one i_power_calu_low(
                                   .sys_clk         (sys_clk         ),
                                   .rst             (rst             ),                 
                                   .I_data_in       (I_data_in       ),  
                                   .I_sync_ok       (I_sync_ok       ),                 
                                   .I_norma_bit_data(I_norma_bit_data),
                                   .I_data_rate     (I_data_rate     ),
                                   .I_cap_data_cnt  (I_cap_data_cnt  ),
                                   .I_high_low_sel  (1'b0            ), //0 calu low power            
                                   .O_power_out     (s_low_power_out )
                                              
       );  
 //--------------------------------------------------------------      
  always @(posedge sys_clk or posedge rst)
  if(rst) 
    begin
      crc_ok_d1 <= 1'b0;
      crc_ok_d2 <= 1'b0;
    end
  else 
     begin
      crc_ok_d1 <= I_crc_check_ok;
      crc_ok_d2 <= crc_ok_d1     ;
    end
       
 assign  crc_ok_rising =  crc_ok_d1 &&(!crc_ok_d2);
 
 
   always @(posedge sys_clk or posedge rst)  //delay 50 clock
	if(rst)
      begin
        delay_shift_reg  <= 64'd0;
        crc_ok_delay     <= 1'b0 ;
      end  
   else 
      begin
        delay_shift_reg[0]    <= crc_ok_rising         ;
        delay_shift_reg[63:1] <= delay_shift_reg[62:0] ;
        crc_ok_delay          <= delay_shift_reg[24]   ;
      end 
 
 
  always @(posedge sys_clk or posedge rst)
  if(rst) 
    begin
      O_power_out <= 16'd0;
      O_hdm960_gc <= 8'd0 ;
    end
  else if(crc_ok_rising)    
     begin
      O_power_out <= s_high_power_out - s_low_power_out ;
      O_hdm960_gc <= I_hdm960_gc ;
    end
    
            
endmodule

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date:    15:33:18 09/28/2010 
// Design Name: 
// Module Name:    dac_inf 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
module power_calu_one(
                input              sys_clk         ,
                input              rst             , 
                
                input   [13:0]     I_data_in       ,  
                input              I_sync_ok       ,
                 
                input              I_norma_bit_data,
                input   [15:0]     I_data_rate     ,
                input   [15:0]     I_cap_data_cnt  ,
                input              I_high_low_sel  , //1 calu high power       
      
                output  reg [15:0] O_power_out     
                                              
       );
                    
                       
//----------------------------------------------------------------

 wire   [15:0]   point_1_4 ;
 wire   [15:0]   point_3_4 ;
 reg             acc_power_en;
 reg             sync_ok_d1 ;
 reg             sync_ok_d2 ;
 wire            sync_ok_rising;
 wire            sync_ok_faling;
 reg             sync_ok_faling_d1;
 reg             sync_ok_faling_d2;
 reg             sync_ok_faling_d3;
 reg             sync_ok_faling_d4;
 reg   [13:0]    s_data_in_d1;
 reg   [13:0]    s_data_in_d2;
 reg   [47:0]    acc_power_data;
 reg   [23:0]    acc_power_num ;
 reg   [23:0]    loc_power_num ; 
 reg   [47:0]    loc_power_data; 
 wire            loc_power_en  ;
 wire  [47:0]    div_result    ;
 wire            div_rdy       ;
 reg   [63:0]    delay_shift_reg;  
 reg             loc_power_delay_en;
 reg             norma_bit_data    ;

//----------------------------------------------------------------

  assign  point_1_4 =  {2'd0,I_data_rate[15:2]};
  assign  point_3_4 =  {2'd0,I_data_rate[15:2]} + {1'd0,I_data_rate[15:1]};

  
//----------------------------------------------------------------
  always @(posedge sys_clk or posedge rst)
  if(rst)
    norma_bit_data <= 1'b0;
  else 
    norma_bit_data <= I_norma_bit_data; 

  always @(posedge sys_clk or posedge rst)
  if(rst)
    acc_power_en <= 1'b0;
  else if(sync_ok_d1 &&(I_cap_data_cnt >= point_1_4)&&(I_cap_data_cnt <= point_3_4)&&(norma_bit_data == I_high_low_sel))
    acc_power_en <= 1'b1;
  else 
    acc_power_en <= 1'b0;
    
    
  always @(posedge sys_clk or posedge rst)
  if(rst) 
    begin
      sync_ok_d1 <= 1'b0;
      sync_ok_d2 <= 1'b0;
    end
  else 
     begin
      sync_ok_d1 <= I_sync_ok;
      sync_ok_d2 <= sync_ok_d1;
    end
       
 assign  sync_ok_rising =  I_sync_ok &&(!sync_ok_d1);
 assign  sync_ok_faling =  sync_ok_d2 &&(!sync_ok_d1);
 
 
 always @(posedge sys_clk or posedge rst)
  if(rst)
    begin
      sync_ok_faling_d1 <= 1'b0;
      sync_ok_faling_d2 <= 1'b0;
      sync_ok_faling_d3 <= 1'b0;
      sync_ok_faling_d4 <= 1'b0;
    end 
  else 
     begin
      sync_ok_faling_d1 <= sync_ok_faling   ;
      sync_ok_faling_d2 <= sync_ok_faling_d1;
      sync_ok_faling_d3 <= sync_ok_faling_d2;
      sync_ok_faling_d4 <= sync_ok_faling_d3;
    end   
 
 always @(posedge sys_clk or posedge rst)
  if(rst)
   begin  
    s_data_in_d1 <= 14'd0;
    s_data_in_d2 <= 14'd0;
   end
  else 
   begin
    s_data_in_d1 <= I_data_in;
    s_data_in_d2 <= s_data_in_d1;
   end
 
  always @(posedge sys_clk or posedge rst)
  if(rst)  
    acc_power_data <= 48'd0;
  else if(sync_ok_rising)
    acc_power_data <= 48'd0;
  else if(acc_power_en)
    acc_power_data <= acc_power_data + {34'd0,s_data_in_d2};
    
  always @(posedge sys_clk or posedge rst)
  if(rst)  
    acc_power_num <= 24'd0;
  else if(sync_ok_rising)
    acc_power_num <= 24'd0;
  else if(acc_power_en)
    acc_power_num <= acc_power_num + 24'd1; 
    
      
  always @(posedge sys_clk or posedge rst)
  if(rst) 
    begin
      loc_power_num  <= 24'd0;
      loc_power_data <= 48'd0;
    end
  else if(sync_ok_faling)
     begin
      loc_power_num  <= acc_power_num ;
      loc_power_data <= acc_power_data;
    end  

 assign loc_power_en = sync_ok_faling_d1;    
 
 //-------delay-----------------------------------------------
  always @(posedge sys_clk or posedge rst)  //delay 50 clock
	if(rst)
      begin
        delay_shift_reg    <= 64'd0;
        loc_power_delay_en <= 1'b0 ;
      end  
   else 
      begin
        delay_shift_reg[0]    <= loc_power_en         ;
        delay_shift_reg[63:1] <= delay_shift_reg[62:0];
        loc_power_delay_en    <= delay_shift_reg[50]  ;
      end 
 
 always @(posedge sys_clk or posedge rst)  //delay 50 clock
	if(rst)
	   O_power_out <= 16'd0;
	else if(div_rdy)
	   O_power_out <= div_result[15:0];
	   
 //----------------------------------------------------------
 
 div_calu i_div_calu(
                  .rfd       (),
                  .clk       (sys_clk       ),
                  .nd        (loc_power_en  ),
                  .dividend  (loc_power_data),
                  .quotient  (div_result    ),
                  .divisor   (loc_power_num ),
                  .rdy       (div_rdy       ),
                  .fractional()
					);
endmodule