计时模块的 VerilogHDL 源代码:
module js(reset,start,clk_1,jishi,jishi_1);
input reset,start,clk_1;
output jishi,jishi_1;
reg [5:0] count1,count2;
reg [7:0] jishi,jishi_1;
always@(negedge reset,posedge clk_1)
begin
if(!reset)
begin
count2=6’b000000;
count1=6’b000000;
jishi=8’b00000000;
jishi_1=8’b00000000;
end
else
begin
if(!start)
begin
if(count16’b000001)
begin
jishi=jishi+8’b00000001;
count2=count2+6’b000001;
count1=count1+6’b000001;
if(count26’b000011)
begin
jishi_1=jishi_1+1’b1;
count2=6’b000000;
end
if(jishi[3:0]>4’b1001)
begin
jishi[7:4]=jishi[7:4]+4’b0001;
jishi[3:0]=4’b0000;
end
end
else if(count1==6’b000010)
count1=6’b000000;
else
count1=count1