硬修复(hPPR)与软修复(sPPR)

什么是PPR?

PPR(Post Package Repair)是一种内存修复技术,主要用于修复DRAM(包括LPDDR4、DDR4等)中的存储单元故障。它通过在封装后对内存芯片进行修复,提高良率和可靠性,减少因制造缺陷导致的内存失效。

        想象一下,你买了一袋苹果,有些苹果表面可能有个小斑点或者磕伤,但你不想因为这些小瑕疵就扔掉整个苹果。内存PPR技术就像是给这些有瑕疵的苹果“做美容”,让它们看起来和好的一样。这里的“内存”就像是那些苹果,而“PPR”就是那个美容师。PPR的全称是Post Package Repair,也就是封装后修复。内存颗粒在生产和使用过程中,可能会因为各种原因出现一些小故障,比如某个存储单元坏了。这时候,PPR技术就派上用场了。

PPR技术有两种主要方式:一种是硬修复(hPPR),另一种是软修复(sPPR)。

  • 硬修复(hPPR):这种方式就像是给苹果做了个“整形手术”。它直接改变了内存里面的电路连接,把坏的地方用好的地方替换掉。这个替换是永久的,就像整形手术一样,一旦做了就无法恢复原样。硬修复的好处是修复后效果持久,但缺点是过程比较复杂,需要点时间。
  • 软修复(sPPR):这种方式就像是给苹果贴了个“创可贴”。它只是暂时改变了内存的工作方式,让坏的地方暂时不被使用,而是用好的地方来替代。这个替代是临时的,如果内存断电或者重启,修复就会失效。软修复的好处是速度快,但缺点是效果不持久。
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The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as sixteen-banks, 4 bank group with 4 banks for each bank group for x4/x8 and eight-banks, 2 bank group with 4 banks for each bankgroup for x16 DRAM. The DDR4 SDRAM uses a 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR4 SDRAM consists of a single 8n-bit wide, four clock data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write operation to the DDR4 SDRAM are burst oriented, start at a selected location, and continue for a burst length of eight or a ‘chopped’ burst of four in a programmed sequence. Operation begins with the registration of an ACTIVATE Command, which is then followed by a Read or Write command. The address bits registered coincident with the ACTIVATE Command are used to select the bank and row to be activated (BG0-BG1 in x4/8 and BG0 in x16 select the bankgroup; BA0-BA1 select the bank; A0-A17 select the row; refer to “DDR4 SDRAM Addressing” on datasheet). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst operation, determine if the auto precharge command is to be issued (via A10), and select BC4 or BL8 mode ‘on the fly’ (via A12) if enabled in the mode register. Prior to normal operation, the DDR4 SDRAM must be powered up and initialized in a predefined manner. The following sections provide detailed information covering device reset and initialization, register definition, command descriptions, and device operation.
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