HDL bits 做题日常--circuits-basic gates

1.wire

module top_module (
    input in,
    output out);
assign out=in;
endmodule

2.GND

module top_module (
    output out);
assign out=1'b0;
endmodule

3.NOR

module top_module (
    input in1,
    input in2,
    output out);
    assign out=~(in1|in2);
endmodule

4.another gate

module top_module (
    input in1,
    input in2,
    output out);
    assign out=in1&(~in2);
endmodule

5.two gates

module top_module (
    input in1,
    input in2,
    input in3,
    output out);
    assign out=(~(in1^in2))^in3;
endmodule

6.more logic gates

module top_module( 
    input a, b,
    output out_and,
    output out_or,
    output out_xor,
    output out_nand,
    output out_nor,
    output out_xnor,
    output out_anotb
);
    assign out_and=a&b, out_or=a|b, out_xor=a^b, out_nand=~(a&b);
    assign out_nor=~(a|b), out_xnor=~(a^b), out_anotb=a&~b;
endmodule

7. 7420 chips

module top_module ( 
    input p1a, p1b, p1c, p1d,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
    assign p1y=~(p1a&p1b&p1c&p1d);
    assign p2y=~(p2a&p2b&p2c&p2d);

endmodule

8.truth tables

module top_module( 
    input x3,
    input x2,
    input x1,  // three inputs
    output f   // one output
);
    assign f=((~x3)&x2&(~x1))|((~x3)&x2&x1)|(x3&x1&(~x2))|(x3&x2&x1);
endmodule

9.two-bit equality

module top_module ( input [1:0] A, input [1:0] B, output z ); 
    assign z=(A==B)? 1'b1:1'b0;
          

            
endmodule

但是，用always语句if else写老错

10.simple circuit A

module top_module (input x, input y, output z);
    assign z=(x^y)&x;
endmodule

11.simple circuit B

module top_module ( input x, input y, output z );
    assign z=(~x&(~y))|(x&y);
endmodule

12.combine circuit A and B

module top_module (input x, input y, output z);
    assign z=(((x^y)&x)|((~x&(~y))|(x&y)))^(((x^y)&x)&((~x&(~y))|(x&y)));
endmodule

13.ringer

module top_module (
    input ring,
    input vibrate_mode,
    output ringer,       // Make sound
    output motor         // Vibrate
);
    assign ringer=ring&(~vibrate_mode);
    assign motor=vibrate_mode˚
endmodule

14.thermostat

module top_module (
    input too_cold,
    input too_hot,
    input mode,
    input fan_on,
    output heater,
    output aircon,
    output fan
); 
assign heater=mode&too_cold;
    assign aircon=~mode&too_hot;
    assign fan=(mode&too_cold)|(~mode&too_hot)|fan_on;
endmodule

15.Popcount3

module top_module( 
    input [2:0] in,
    output [1:0] out );
    integer n;
    always@(in) begin
    out = 0;
    for(n=0;n<3;n=n+1)
    out=out+in[n];
    end
endmodule

16.gatesv

out_different 异或

module top_module( 
    input [3:0] in,
    output [2:0] out_both,
    output [3:1] out_any,
    output [3:0] out_different );
    assign out_both={in[2]&in[3],in[2]&in[1],in[1]&in[0]};
    assign out_any={in[3]|in[2],in[1]|in[2],in[1]|in[0]};
    assign out_different={in[3]^in[0],in[3]^in[2],in[2]^in[1],in[1]^in[0]};
endmodule

17.Gatesv100

(太高级了 需要多次感受）

module top_module( 
    input [99:0] in,
    output [98:0] out_both,
    output [99:1] out_any,
    output [99:0] out_different );
    assign out_both      = in[98:0] & in[99:1];
    assign out_any       = in[99:1] | in[98:0];
    assign out_different = in[99:0] ^ {in[0],in[99:1]};

       
endmodule