HDL bits--circuits--sequential logic--latches and flip-flops

1.Dff

在clk always 模块中 始终用非阻塞

module top_module (
    input clk,    // Clocks are used in sequential circuits
    input d,
    output reg q );//
    always@(posedge clk) begin
        q<=d;
    end

    // Use a clocked always block
    //   copy d to q at every positive edge of clk
    //   Clocked always blocks should use non-blocking assignments

endmodule

2.Dff8

module top_module (
    input clk,
    input [7:0] d,
    output [7:0] q
);
    always@(posedge clk) begin
        q<=d;
    end
endmodule

3.Dff8r

module top_module (
    input clk,
    input reset,            // Synchronous reset
    input [7:0] d,
    output [7:0] q
);
    always@(posedge clk) begin
        if(reset)
            q<=0;
        else
            q<=d;
    end
        
endmodule

4.dff8p

(这题题目没看懂）

module top_module (
    input clk,
    input reset,
    input [7:0] d,
    output [7:0] q
);
    always@(negedge clk) begin
        if(reset)
            q<=8'h0x34;
        else
            q<=d;
    end
endmodule

5.Dff8ar

module top_module (
    input clk,
    input areset,   // active high asynchronous reset
    input [7:0] d,
    output [7:0] q
);
    always@(posedge clk or posedge areset) begin
        if (areset)
            q<=0;
        else
            q<=d;
    end
       
endmodule

6.Dff16e

(我靠 第一个 错的，第二个代码是对的）但是为什么啊？使能端都为0的话，输出不应该是0吗？

module top_module (
    input clk,
    input resetn,
    input [1:0] byteena,
    input [15:0] d,
    output [15:0] q
);
    always@(posedge clk) begin
        if(!resetn)
            q<=0;
        else begin
            case(byteena)
                2'b00:q<=0;
                2'b01:q[7:0]<=d[7:0];
                2'b10:q[15:8]<=d[15:8];
                2'b11:q<=d;
            endcase
        end
    end
                
endmodule

module top_module (
    input clk,
    input resetn,
    input [1:0] byteena,
    input [15:0] d,
    output [15:0] q
);
always @(posedge clk) begin
	if(!resetn)
		q <= 16'd0;
	else begin
		case(byteena)     // 这里用if..else if..else if..else这种写法也是可以的
			2'b00: q <= q;
			2'b01: q[7:0] <= d[7:0];
			2'b10: q[15:8] <= d[15:8];
			2'b11: q <= d;
		endcase
	end	
end


                
endmodule

我不明白当byteena是01的时候，q的[15:8]不用管吗？原来这种语句也可以嵌套，记得写begin.

7. d latch

module top_module (
    input d, 
    input ena,
    output q);
    always@(ena) begin
        if(ena)
            q<=d;
        else
            q<=q;
    end       
endmodule

8.dff

module top_module (
    input clk,
    input d, 
    input ar,   // asynchronous reset
    output q);
    always@(posedge clk or posedge ar) begin
        if(ar)
            q<=0;
        else
            q<=d;
    end
endmodule

9.dff

module top_module (
    input clk,
    input d, 
    input r,   // synchronous reset
    output q);
    always@(posedge clk) begin
        if(r)
            q<=0;
        else
            q<=d;
    end
endmodule

10.dff+gate

module top_module (
    input clk,
    input in, 
    output out);
    reg d;
    assign d=in^out;
    always@(posedge clk) begin
        out<=d;
    end
endmodule

11.mux and dff

module top_module (
	input clk,
	input L,
	input r_in,
	input q_in,
	output reg Q);
    reg d;
    always@(L) begin
        if(L)
            d<=r_in;
        else
            d<=q_in;
    end
    always@(posedge clk) begin
            Q<=d;
    end
endmodule

12.mux and dff

module top_module (
    input clk,
    input w, R, E, L,
    output Q
);
    wire w1;
    reg d;
    assign w1=(E?w:Q);
    assign d=(L?R:w1);
    always@(posedge clk) begin
        Q<=d;
    end
endmodule

13.dffs and gates

module top_module (
    input clk,
    input x,
    output z
); 
    reg d1,d2,d3,Q1,Q2,Q3;
    assign d1=x^Q1;
    assign d2=x&(~Q2);
    assign d3=x|(~Q3);
    always@(posedge clk) begin
        Q1<=d1;
        Q2<=d2;
        Q3<=d3;
    end
    assign z=(~(Q1|Q2|Q3));
endmodule

14.Exams/ece241 2013 q7

module top_module (
    input clk,
    input j,
    input k,
    output Q); 
    
    always@(posedge clk) begin
        Q<=(j&(~Q))|((~k)&Q);
    end           
endmodule

15.Edgedetect

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] pedge
);
    reg [7:0]dff;
   
    always@(posedge clk) begin
      dff<=in;
        pedge<=(~dff)&in;
    end
endmodule

不要忘记之前写那么多寄存器是干嘛用的

16.Edgedetect2

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);
    reg [7:0] dff;
    always@(posedge clk) begin
        dff<=in;
        anyedge<=(dff&(~in))|((~dff)&in);
    end
endmodule

我其实蛮不懂的，为什么不能写下降沿啊

17.Edgecapture

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);
    reg[31:0] dff;
    always@(posedge clk) begin
        dff<=in;
        if (reset)
            out<=0;
        else          
        out<=(dff&(~in))|out;
    end
endmodule

18.Dualedge

module top_module (
    input clk,
    input d,
    output q
);
    reg dff1,dff2;  
    always@(posedge clk) begin
       dff1<=d;
    end
    always@(negedge clk) begin
        dff2<=d;  
    end
    assign q=clk?dff1:dff2;
endmodule

注意观察图像