HDL bits--verification--writing Tb

1.Tb/clock

module top_module();
    

    reg clk;

   initial clk=0;

always
    #5 clk=~clk;

dut instance1(clk);
endmodule

2.Tb/tb1

module top_module ( output reg A, output reg B );//

    // generate input patterns here
    initial begin

        A=0;
        B=0;
        #10 A=1;
        #5 	B=1;
        #5 	A=0;
        #20	B=0;

    end

    

endmodule

3.Tb/and

module top_module();
    reg [1:0] in;
    
    wire out;
    initial begin
        in=2'b00;
      
   
   
        #10 in=2'b01;
        #10 in=2'b10;
        #10 in=2'b11;
    end
    
    andgate instance1(in,out);
endmodule

4.Tb/tb2

module top_module();
    reg clk;
    reg in;
    reg [2:0] s;
    wire out;
  initial 
        begin
            clk=0;
            s=2;
            in=0;
            #10 s=6;
            #10 s=2;in=1;
            #10 s=7;in=0;
            #10 s=0;in=1;
            #30 in=0;
           
        end
             
 always begin #5 clk=~clk;end          
            
            q7 instance1(clk,in,s,out);
endmodule

5.Tb/tff

module top_module ();
 
    reg clk,t,q,reset;
    
    tff tff_1(.clk(clk),.reset(reset), .t(t),.q(q));
    initial begin
          clk=0;
        forever
        #4//不一定非得是5
        clk=~clk;
    end
  initial begin
        reset = 1'b0;
        #3
        reset = 1'b1;
        #10//要根据时钟那里来变
        reset = 1'b0;   
  end
     always@(posedge clk)begin
        if(reset)begin
            t <= 1'b0;
        end
        else begin
            t <= 1'b1;
        end
     end
endmodule

这个没写出来 是看别的博主的代码