HDL bits--Reading simulations--finding bugs

最新推荐文章于 2024-08-17 23:54:07 发布

fluffysusu

最新推荐文章于 2024-08-17 23:54:07 发布

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文章标签： fpga开发

本文链接：https://blog.csdn.net/fluffysusu/article/details/136467218

版权

本文详细介绍了五个Verilog模块，包括多路选择器Bugsmux、与非门Bugsnand、多输入选择器mux、加减运算器Bugsaddsubz以及条件分支处理Bugscase，展示了基础逻辑门和控制结构在硬件描述语言中的应用。

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1.Bugs mux2

module top_module (
    input sel,
    input [7:0] a,
    input [7:0] b,
    output [7:0] out  );
    
    assign out =sel?a:b;
    

endmodule

2.Bugs nand3

module top_module (input a, input b, input c, output out);//
wire out1;
    andgate inst1 ( out1, a, b, c,1'b1,1'b1 );
    assign out=~out1;
    

endmodule

3.Bugs mux4

module top_module (
    input [1:0] sel,
    input [7:0] a,
    input [7:0] b,
    input [7:0] c,
    input [7:0] d,
    output [7:0] out  ); //

    reg [7:0] mux0;
    reg [7:0] mux1;
    mux2 instance0 ( sel[0],    a,    b, mux0 );
    mux2 instance1 ( sel[0],    c,    d, mux1 );
    mux2 instance2 ( sel[1], mux0, mux1,  out );

endmodule

4.Bugs addsubz

module top_module ( 
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output reg result_is_zero
);//

    always @(*) begin
        case (do_sub)
          1'b0: out = a+b;
          1'b1: out = a-b;
        endcase

        if (out==8'h0)
            result_is_zero <= 1'b1;
        else
            result_is_zero<=1'b0;
    end

endmodule

5.Bugs case

module top_module (
    input [7:0] code,
    output reg [3:0] out,
    output reg valid );//

    always @(*)
        case (code)
            8'h45: begin
                valid = 1;
                  out = 0;
            end
            8'h16: begin
                valid = 1;
                  out = 1;
            end
            8'h1e: begin
                valid = 1;
                  out = 2;
            end
            8'h26: begin
                valid = 1;
                  out = 3;
            end
            8'h25: begin
                valid = 1;
                  out = 4;
            end
            8'h2e: begin
                valid = 1;
                  out = 5;
            end
            8'h36: begin
                valid = 1;
                  out = 6;
            end
            8'h3d: begin
               valid = 1;
                 out = 7;
            end
            8'h3e: begin
               valid = 1;
                 out = 8;
            end
            8'h46: begin
               valid = 1;
                 out = 9;
            end
            default: begin
               valid = 0;
                 out = 0;
            end
        endcase

endmodule