HDL bits---circuits---counters

最新推荐文章于 2024-10-17 16:08:47 发布

fluffysusu

最新推荐文章于 2024-10-17 16:08:47 发布

阅读量401

点赞数 7

文章标签： fpga开发

本文链接：https://blog.csdn.net/fluffysusu/article/details/136306172

版权

这篇文章详细描述了几种Verilog模块的设计，包括简单的计数器、BCD编码计数器以及模拟时钟和时间显示功能，展示了同步复位、进位控制和组合逻辑的运用。

摘要由CSDN通过智能技术生成

1.Count15

module top_module (
    input clk,
    input reset,      // Synchronous active-high reset
    output [3:0] q);
    always@(posedge clk) begin
        if(reset)
            q<=0;
        else 
                q<=q+1;
           
    end
endmodule

2.Count10

module top_module (
    input clk,
    input reset,        // Synchronous active-high reset
    output [3:0] q);
    always@(posedge clk) begin
        if (reset)
            q<=0;
        else
            q<=q+1;
        case(q)
            4'b1010,4'b1011,4'b1100,4'b1101,4'b1110,4'b1111,4'b1001:q<=0;
        endcase
    end
endmodule

module top_module(
	input clk,
	input reset,
	output reg [3:0] q);
	
	always @(posedge clk)
		if (reset || q == 9)	// Count to 10 requires rolling over 9->0 instead of the more natural 15->0
			q <= 0;
		else
			q <= q+1;
	
endmodule

3.Count1to10

module top_module (
    input clk,
    input reset,
    output [3:0] q);
    always@(posedge clk) begin
        if (reset||q==10)
            q<=1;
        else
            q<=q+1;
    end
endmodule

4.Countslow

module top_module (
    input clk,
    input slowena,
    input reset,
    output [3:0] q);

    always@(posedge clk) begin
       
        if(reset)
            q<=0;
        else if(q >= 4'b1001 && slowena)
             q<=0;
            else if(slowena)
            q<=q+1;
        else
            q<=q;
        
    end
endmodule

5.Exams/ece241 2014 q7a

module top_module (
    input clk,
    input reset,
    input enable,
    output [3:0] Q,
    output c_enable,
    output c_load,
    output [3:0] c_d
); //
   assign c_enable=enable;
    /*
    always@(posedge clk) begin
        if(reset||Q>=12) begin
            c_load<=0;
            c_d<=1;
        end
        else
            c_load<=1;
    end
    */
    assign c_load=(reset||(Q>=12&&enable)) ? 1:0;
    assign c_d=c_load;
    count4 the_counter (clk, c_enable, c_load, c_d,Q);


    

endmodule

这题我完全看不懂他什么意思，这个代码是看别人的。

6.Exams/ece241 2014 q7b6.

module top_module (
    input clk,
    input reset,
    output OneHertz,
    output [2:0] c_enable
); //    
  
    reg [3:0] q0,q1,q2;
    always @(*) begin
        if(reset) begin
            c_enable <= 3'b000;
        end
        else begin
            c_enable[0] = 1'b1;
            if(q0==4'd9) 
                c_enable[1] = 1'b1;
            else 
                c_enable[1] = 1'b0;
            if(q1==4'd9 && q0==4'd9)
                c_enable[2] = 1'b1;
            else 
                c_enable[2] = 1'b0; 
            
        end
    end
    assign OneHertz = (q2==4'd9 && q1==4'd9 && q0==4'd9);   
    
        
    bcdcount counter0 (clk, reset, c_enable[0],q0);
    bcdcount counter1 (clk, reset, c_enable[1],q1);
    bcdcount counter2 (clk, reset, c_enable[2],q2);

            

endmodule

醍醐灌顶，我一直在想进位信号是不是要自己设计，结果原来使能端就是进位信号。

所以写了很久。

7.Countbcd

module top_module (
    input clk,
    input reset,   // Synchronous active-high reset
    output [3:1] ena,
    output [15:0] q);
wire  [3:0] ge,shi,bai,qian; //定义4位的个、十、百、千
    
    //因为个位一直有，所以单独赋值
    always@(posedge clk) begin
        if (reset == 1'b1)
            ge <= 4'd0;
        else if(ge == 4'd9)
            ge <= 4'd0;
        else
            ge <= ge + 1'b1; 
    end
    
    assign q = {qian,bai,shi,ge};  //使用组合逻辑，立即输出
    //assign ena={ena[3],ena[2],ena[1]}; 可要可不要，因为后面已经对输出的每一位赋值了
    assign ena[1] = (ge == 4'd9) ? 1 : 0; 
    assign ena[2] = (shi == 4'd9 && ge == 4'd9) ? 1:0;
    assign ena[3] = (bai == 4'd9 && shi == 4'd9 && ge == 4'd9) ? 1 : 0;
    
    //例化模块
    counter10bcd counter10bcd_inst2(clk,ena[1],reset,shi);
    counter10bcd counter10bcd_inst3(clk,ena[2],reset,bai);
    counter10bcd counter10bcd_inst4(clk,ena[3],reset,qian);
        
endmodule

module counter10bcd (
    input clk,
    input ena,
    input reset,
    output [3:0] q);
    
    //同步复位
    always @(posedge clk) begin
        if (reset == 1'b1)
            q <= 4'd0;
        else if(ena == 1'b1) begin
            if (q == 4'd9)
                q <= 4'd0;
            else
                q <= q + 1'b1;
        end
        else
            q <= q;      
    end
endmodule

这个是看别人的，自己没写出来。写题的时候思路要清晰，要例化就例化。

8.Count clock

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm, 
    output [7:0] ss); 
    reg [3:0] ss_ge,ss_shi;        //秒钟上的个位与十位
    reg [3:0] mm_ge,mm_shi;        //分钟上的个位与十位
    reg [3:0] hh_ge,hh_shi;        //小时上的个位与十位

 /*===========================================================
     秒钟上 个位与十位的编写
     个位：在使能有效的情况下，进行判断如果计数到9，回零，
          否则自加1，其余情况保持原态
     十位：在使能有效并且个位为9的情况下，进行判断如果计数到9，回零，
          否则自加1，其余情况保持原态
 ============================================================*/   
    always @(posedge clk) begin
        if (reset == 1'b1)
            ss_ge <= 4'd0;
        else if(ena == 1'b1) begin
            if (ss_ge == 4'd9)
                ss_ge <= 4'd0;
            else
                ss_ge <= ss_ge + 1'b1;
        end
        else
            ss_ge <= ss_ge;      
    end

    always @(posedge clk) begin
        if(reset == 1'b1)
            ss_shi <= 4'd0;
        else if(ena == 1'b1 && ss_ge == 4'd9) begin
            if(ss_shi == 4'd5)
                ss_shi <= 4'd0;
            else
                ss_shi <= ss_shi + 1'b1;
        end
        else
            ss_shi <= ss_shi;
    end
 /*=====================================================
  	分钟上 个位与十位的编写
  	个位：在秒为59时，并且使能有效情况下，才进行判断
  	十位：在秒为59时，分钟的个位为9，并且使能有效情况下，才进行判断
 ======================================================*/  
    always @(posedge clk) begin
        if (reset == 1'b1)
            mm_ge <= 4'd0;
        else if(ena == 1'b1 && ss_shi == 4'd5 && ss_ge == 4'd9) begin
            if (mm_ge == 4'd9)
                mm_ge <= 4'd0;
            else
                mm_ge <= mm_ge + 1'b1;
        end
        else
            mm_ge <= mm_ge;      
    end

    always @(posedge clk) begin
        if(reset == 1'b1)
            mm_shi <= 4'd0;
        else if(ena == 1'b1 && mm_ge == 4'd9 && ss_shi == 4'd5 && ss_ge == 4'd9 ) begin
            if(mm_shi == 4'd5)
                mm_shi <= 4'd0;
            else
                mm_shi <= mm_shi + 1'b1;
        end
        else
            mm_shi <= mm_shi;
    end
 /*=========================================
     小时上 个位与十位的编写
     个位：在秒与分均为59，并使能有效的情况下，进行判断
   		  如果小时显示12，回归初态，初值为1
   		  如果小时个位计数到9，回归初态0，否则，自加1
   		  其他情况，保持当前状态
     十位：在秒与分均为59，并使能有效的情况下，进行判断
     	  如果小时显示12，回归初态，初值为0
     	  如果个位上的数计数到9，自加1
     	  其他情况，保持当前状态
 ==========================================*/     
    always @(posedge clk) begin
        if (reset == 1'b1)
            hh_ge <= 4'd2;
        else if(ena == 1'b1 && mm_shi == 4'd5 && mm_ge == 4'd9 && ss_shi == 4'd5 && ss_ge == 4'd9) begin
            if (hh_shi == 4'd1 && hh_ge == 4'd2)
                hh_ge <= 4'd1;
            else if (hh_ge == 4'd9)
                hh_ge <= 4'd0;
            else
                hh_ge <= hh_ge + 1'b1;
        end
        else
            hh_ge <= hh_ge;      
    end

    always @(posedge clk) begin
        if(reset == 1'b1)
            hh_shi <= 4'd1;
        else if(ena == 1'b1 && mm_shi == 4'd5 && mm_ge == 4'd9 && ss_shi == 4'd5 && ss_ge == 4'd9) begin
            if(hh_shi == 4'd1 && hh_ge == 4'd2)
                hh_shi <= 4'd0;
            else if(hh_ge == 4'd9)
                hh_shi <= hh_shi + 1'b1;
        end
        else 
            hh_shi <= hh_shi;
    end
 /*=========================================
     判别上午与下午标志位的编写
     当使能有效，并且显示11:59:59时，翻转pm的状态
 ==========================================*/      
    always @(posedge clk) begin
        if(reset == 1'b1)
            pm <= 1'b0;
        else if(ena == 1'b1 && hh_shi == 4'd1 &&hh_ge == 4'd1 && mm_shi == 4'd5 && mm_ge == 4'd9 && ss_shi == 4'd5 && ss_ge == 4'd9)
            pm <= ~pm;
        else 
            pm <= pm;
    end
 /*=========================================
    使用位拼接将秒，分钟，小时表示出来
 ==========================================*/       
    assign ss = {ss_shi,ss_ge};   
    assign mm = {mm_shi,mm_ge};
    assign hh = {hh_shi,hh_ge};
    
endmodule

太高级了我说这个也是看别的博主的