1,verilog仿真语法模版_时钟激励

FPGA小飞

已于 2024-09-07 09:50:52 修改

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分类专栏： verilog仿真文章标签： fpga开发

于 2024-09-07 09:44:09 首次发布

本文链接：https://blog.csdn.net/fpga_love/article/details/141987349

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Clock stimulus

1,50%占空比单端时钟

1)使用always

   // Note: CLK must be defined as a reg when using this method

   parameter PERIOD = <value>;

   always begin

      CLK = 1'b0;

      #(PERIOD/2) CLK = 1'b1;

      #(PERIOD/2);

   end

2)使用forever

// Note: CLK must be defined as a wire when using this method

   parameter PERIOD = <value>;

   initial begin

      CLK = 1'b0;

      #(PERIOD/2);

      forever

         #(PERIOD/2) CLK = ~CLK;

   end

2,非50%占空比单端时钟

1)使用always

  // Note: CLK must be defined as a reg when using this method

   parameter PERIOD = <value>;

   parameter DUTY_CYCLE = <value_0.01_to_0.99>;

   always begin

      CLK = 1'b0;

      #(PERIOD-(PERIOD*DUTY_CYCLE)) CLK = 1'b1;

      #(PERIOD*DUTY_CYCLE);

   end

2)使用forever

   // Note: CLK must be defined as a wire when using this method

   parameter PERIOD = <value>;

   parameter DUTY_CYCLE = <value_0.01_to_0.99>;

   initial

      forever begin

         CLK = 1'b0;

         #(PERIOD-(PERIOD*DUTY_CYCLE)) CLK = 1'b1;

         #(PERIOD*DUTY_CYCLE);

      end

3,50%占空比差分时钟

1)使用always

   // Note: CLK_P and CLK_N must be defined as a reg when using this method

   parameter PERIOD = <value>;

   always begin

      CLK_P = 1'b0;

      CLK_N = 1'b1;

      #(PERIOD/2) CLK_P = 1'b1;

      CLK_N = 1'b0;

      #(PERIOD/2);

   end

2)使用forever

// Note: CLK_P and CLK_N must be defined as a wire when using this method

   parameter PERIOD = <value>;

   initial begin

      CLK_P = 1'b0;

      CLK_N = 1'b1;

      #(PERIOD/2);

      forever

         #(PERIOD/2) {CLK_P, CLK_N} = ~{CLK_P, CLK_N};

   end

4,非50%占空比差分时钟

1)使用always

 // Note: CLK_P and CLK_N must be defined as a reg when using this method

   parameter PERIOD = <value>;

   parameter DUTY_CYCLE = <value_0.01_to_0.99>;

   always begin

      CLK_P = 1'b0;

      CLK_N = 1'b1;

      #(PERIOD-(PERIOD*DUTY_CYCLE)) CLK_P = 1'b1;

      CLK_N = 1'b0;

      #(PERIOD*DUTY_CYCLE);

   end

2)使用forever

// Note: CLK_P and CLK_N must be defined as a wire when using this method

   parameter PERIOD = <value>;

   parameter DUTY_CYCLE = <value_0.01_to_0.99>;

   initial

      forever begin

         CLK_P = 1'b0;

         CLK_N = 1'b1;

         #(PERIOD-(PERIOD*DUTY_CYCLE)) CLK_P = 1'b1;

         CLK_N = 1'b0;

         #(PERIOD*DUTY_CYCLE);

      end

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