HDLBits 刷题之我的代码（全）—（Circuits-Building Lager Circuits）

#1

module top_module (
    input clk,
    input reset,
    output [9:0] q);
    always @(posedge clk) begin
        if(reset == 'd1) begin
            q <= 'd0;
        end
        else begin
            if(q == 'd999) begin
                q <= 'd0;
            end
            else begin
                q <= q + 'd1;
            end
        end
    end
endmodule

#2

module top_module (
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output [3:0] q);
    always @(posedge clk) begin
        if(shift_ena == 'd1) begin
            q <= (q << 1) + data;
        end
        else if(count_ena == 'd1) begin
        	q <= q - 'd1;
        end
        else begin
        	q <= q;
        end
    end    
endmodule

#3

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output start_shifting);
	parameter  s0   =   'b00001,
               s1   =   'b00010,
               s2   =   'b00100,
               s3   =   'b01000,
               s4   =   'b10000;
    reg [5:0] state,nstate;
    always @(posedge clk) begin
        if(reset == 'd1) begin
            state <= s0;
        end
        else begin
            state <= nstate;
        end
    end
    always @(*) begin
        case(state)
            s0: begin
                if(data == 'd1) 
                    nstate <= s1;
                else
                	nstate <= s0;        
            end
            s1: begin
                if(data == 'd1) 
                    nstate <= s2;
                else
                    nstate <= s0;    
            end
            s2: begin
                if(data == 'd1) 
                    nstate <= s2;
                else
                    nstate <= s3;     
            end
            s3: begin
                if(data == 'd1) 
                    nstate <= s4;
                else
                    nstate <= s0;    
            end
            s4: begin
                nstate <= s4;
            end                    
            default: nstate <= s0;
        endcase
    end
    assign start_shifting = (state == s4);
endmodule

#4

module top_module (
    input clk,
    input reset,      // Synchronous reset
    output shift_ena);
    reg [3:0]count;
    parameter s1 = 'b01,
    	      s2 = 'b10;
    reg [1:0] state;
    always @(posedge clk) begin
        if(reset == 'd1) begin
            count <= 'd0;
            shift_ena <= 'd1;
        end
        else begin
            shift_ena <= shift_ena;
            if(count == 'd3) begin
                count <= count; 
                shift_ena <= 'd0;
            end
            else 
                count <= count + 'd1;
    
        end
    end
endmodule

#5

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output shift_ena,
    output counting,
    input done_counting,
    output done,
    input ack );
	parameter   S		=		10'b0000000001,  
    			S1	 	=		10'b0000000010,
    			S11 	=		10'b0000000100,
    			S110 	=		10'b0000001000,
    			B0		=		10'b0000010000, 
    			B1  	=		10'b0000100000,
    			B2  	=		10'b0001000000,
    			B3  	=		10'b0010000000,
    			Count   =		10'b0100000000,
    			Wait	=		10'b1000000000;
    reg [9:0] state,nstate;
    always @(posedge clk) begin
        if(reset == 'd1) begin
            state <= S;
        end
        else begin
            state <= nstate;
        end
    end
    always @(*) begin
        case(state)
            S: begin
                if(data == 'd1) begin
                    nstate = S1;
                end
                else begin
                    nstate = S;
                end
            end
            S1: begin
                if(data == 'd1) begin
                    nstate = S11;
                end
                else begin
                    nstate = S;
                end
            end 
            S11:begin
                if(data == 'd1) begin
                    nstate = S11 ;
                end
                else begin
                    nstate = S110;
                end
            end
            S110:begin
                if(data == 'd1) begin
                    nstate = B0;
                end
                else begin
                    nstate = S;
                end
            end
            B0: nstate = B1;
            B1: nstate = B2;
            B2: nstate = B3;
            B3: nstate = Count;
            Count:begin
                if(done_counting == 'd1) begin
                    nstate = Wait;
                end
                else begin
                    nstate = Count;
                end
            end 
            Wait:begin
                if(ack == 'd1) begin
                    nstate = S;
                end
                else begin
                    nstate = Wait;
                end
            end             
            default:state = S;
        endcase
    end
    assign  shift_ena = (state==B0 || state==B1 || state==B2 || state==B3);
    assign  counting = (state==Count);
    assign  done = (state== Wait);  
endmodule

#6

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output [3:0] count,
    output counting,
    output done,
    input ack );
	parameter   S		=		10'b0000000001,  
    			S1	 	=		10'b0000000010,
    			S11 	=		10'b0000000100,
    			S110 	=		10'b0000001000,
    			B0		=		10'b0000010000, 
    			B1  	=		10'b0000100000,
    			B2  	=		10'b0001000000,
    			B3  	=		10'b0010000000,
    			Count   =		10'b0100000000,
    			Wait	=		10'b1000000000;
    reg [9:0] state,nstate;
    always @(posedge clk) begin
        if(reset == 'd1) begin
            state <= S;
        end
        else begin
            state <= nstate;
        end
    end
    always @(*) begin
        case(state)
            S: begin
                if(data == 'd1) begin
                    nstate = S1;
                end
                else begin
                    nstate = S;
                end
            end
            S1: begin
                if(data == 'd1) begin
                    nstate = S11;
                end
                else begin
                    nstate = S;
                end
            end 
            S11:begin
                if(data == 'd1) begin
                    nstate = S11 ;
                end
                else begin
                    nstate = S110;
                end
            end
            S110:begin
                if(data == 'd1) begin
                    nstate = B0;
                end
                else begin
                    nstate = S;
                end
            end
            B0: nstate = B1;
            B1: nstate = B2;
            B2: nstate = B3;
            B3: nstate = Count;
            Count:begin
                if(count == 'd0  && cnt == 'd999) begin
                    nstate = Wait;
                end
                else begin
                    nstate = Count;
                end
            end 
            Wait:begin
                if(ack == 'd1) begin
                    nstate = S;
                end
                else begin
                    nstate = Wait;
                end
            end             
            default:state = S;
        endcase
    end
    reg [9:0] cnt;
    always @(posedge clk) begin
        if(reset == 'd1) begin
            count <= 'd0;
            cnt <= 'd0;
        end
        else begin
            case(state)
                B0: count[3] <= data;
                B1: count[2] <= data;
                B2: count[1] <= data;
                B3: count[0] <= data;
            	Count:	begin
                    if(count >= 'd0) begin
                        if(cnt <= 'd998) begin
                            cnt <= cnt + 'd1;
                        end
                        else begin
                            cnt <= 'd0;
                            count = count - 'd1;
                        end
                    end
                    else begin
                    	count <= 'd0;
            			cnt <= 'd999;    
                    end
                end
            	default: begin
            		count <= 'd0;
            		cnt <= 'd0;                    
                end
        	endcase
    	end
    end
    assign  counting = (state==Count);
    assign  done = (state== Wait); 
endmodule
        

#7

module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
); //

    // You may use these parameters to access state bits using e.g., state[B2] instead of state[6].
    parameter S=0, S1=1, S11=2, S110=3, B0=4, B1=5, B2=6, B3=7, Count=8, Wait=9;

    assign B3_next = state[B2];
    assign S_next =  (state[S] &(~d)) || (state[S1] &(~d)) || (state[S110] &(~d)) || (state[Wait] &(ack));
    // assign S_next = ...;
    assign S1_next = (state[S] &(d));
    assign Count_next = (state[B3]) || (state[Count] &(!done_counting));
    assign Wait_next = (state[Wait] & (~ack)) || (state[Count] &(done_counting));
    assign done = state[Wait];
    assign counting = state[Count];
    assign shift_ena = state[B0] || state[B1] || state[B2] || state[B3] ;
    // etc.

endmodule