HDLBits个人刷题详解合集7-Circuits-Combinational Logic-Multplexers-HDBits题目分析

Mux2to1

Create a one-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.

代码如下：

module top_module(

    input a, b, sel,

    output out );

    assign out = (sel)?b:a;

endmodule

参考答案：

module top_module(

    input a, b, sel,

    output out );

    assign out = （sel&b）| (~sel&a);

endmodule

Mux2to1v

Create a 100-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.

代码如下：

module top_module(

    input [99:0] a, b,

    input sel,

    output [99:0] out );

    assign out = sel?b:a;

endmodule

Mux9to1v

Create a 16-bit wide, 9-to-1 multiplexer. sel=0 chooses a, sel=1 chooses b, etc. For the unused cases (sel=9 to 15), set all output bits to '1'.

我的解决办法：

module top_module(

    input [15:0] a, b, c, d, e, f, g, h, i,

    input [3:0] sel,

    output [15:0] out );

    always @(*)

        begin

                case(sel)

                 4'b0000:out=a;

                    4'b0001:out=b;

                    4'b0010:out=c;

                    4'b0011:out=d;

                    4'b0100:out=e;

                    4'b0101:out=f;

                    4'b0110:out=g;

                    4'b0111:out=h;

                    4'b1000:out=i;

                    default:out = 16'b1111111111111111;// 参考答案：out = '1;

                endcase

            end

endmodule

Mux256to1

Create a 1-bit wide, 256-to-1 multiplexer. The 256 inputs are all packed into a single 256-bit input vector. sel=0 should select in[0], sel=1 selects bits in[1], sel=2 selects bits in[2], etc.

代码如下:

module top_module(

    input [255:0] in,

    input [7:0] sel,

    output out );

    assign out = in[sel];

endmodule

Mux256to1v

Create a 4-bit wide, 256-to-1 multiplexer. The 256 4-bit inputs are all packed into a single 1024-bit input vector. sel=0 should select bits in[3:0], sel=1 selects bits in[7:4], sel=2 selects bits in[11:8], etc.

代码如下：

module top_module(

    input [1023:0] in,

    input [7:0] sel,

    output [3:0] out );

    assign out = in[4*sel+3-:4];//verilog语言中没有这种写法in[(4*sel)+3:(4*sel)]但与前面的写法表示意义相同

endmodule

还有一种清晰明了的写法：

assign out = {in[sel*4+3], in[sel*4+2], in[sel*4+1], in[sel*4+0]};