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HDLBits
glassy__sky
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HDLBits 刷题之我的代码(全)—(Verification:Writing Testbenches)
#1`timescale 1ps/1psmodule top_module ( ); reg clk; initial begin clk = 'b0; forever #5 clk = ~clk; end dut dut1(.clk(clk));endmodule#2`timescale 1ps/1psmodule top_module ( output reg A, output reg B );//原创 2021-03-28 13:10:19 · 159 阅读 · 0 评论 -
HDLBits 刷题之我的代码(全)—(Verification_Reading Simulations-Build a circuit from a simulation waveform)
#1module top_module ( input a, input b, output q );// assign q = a & b; // Fix meendmodule#2module top_module ( input a, input b, input c, input d, output q );// assign q = ((~a) & (~b) & (~c) &a原创 2021-03-28 13:09:56 · 136 阅读 · 0 评论 -
HDLBits 刷题之我的代码(全)—(Verification:Reading Simulations-Finding bugs in codes)
#1module top_module ( input sel, input [7:0] a, input [7:0] b, output [7:0] out ); assign out = ({8{sel}} & a) | ({8{~sel}} & b);endmodule#2module top_module (input a, input b, input c, output out);// wire out_reg;原创 2021-03-28 13:09:15 · 102 阅读 · 0 评论 -
HDLBits 刷题之我的代码(全)—(Circuits-Building Lager Circuits)
#1module top_module ( input clk, input reset, output [9:0] q); always @(posedge clk) begin if(reset == 'd1) begin q <= 'd0; end else begin if(q == 'd999) begin q <= 'd0;原创 2021-03-28 13:08:52 · 74 阅读 · 0 评论 -
HDLBits 刷题之我的代码(全)—(Circuits-Sequential Logic-Finite State Machines)
#1module top_module ( input clk, input reset, output [9:0] q); always @(posedge clk) begin if(reset == 'd1) begin q <= 'd0; end else begin if(q == 'd999) begin q <= 'd0;原创 2021-03-28 13:08:27 · 119 阅读 · 0 评论 -
HDLBits 刷题之我的代码(全)—(Circuits-Sequential Logic-More Circuits)
#1module top_module( input clk, input load, input [511:0] data, output [511:0] q ); reg [511:0] q1; always @(posedge clk) begin if(load == 'd1) begin q <= data; end else begin q原创 2021-03-28 13:08:08 · 78 阅读 · 0 评论 -
HDLBits 刷题之我的代码(全)—(Circuits-Sequential Logic-Shift Registers)
#1module top_module( input clk, input areset, // async active-high reset to zero input load, input ena, input [3:0] data, output reg [3:0] q); always @(posedge clk or posedge areset) begin if(areset) begin原创 2021-03-28 13:07:37 · 98 阅读 · 0 评论 -
HDLBits 刷题之我的代码(全)—(Circuits-Sequential Logic-Counters)
#1module top_module ( input clk, input reset, // Synchronous active-high reset output [3:0] q); always @(posedge clk) begin:counter if(reset == 'd1) begin q <= 'd0; end else begin q &原创 2021-03-28 13:06:56 · 102 阅读 · 0 评论 -
HDLBits 刷题之我的代码(全)—(Verilog Language-Sequential Logic-Latches and Flip_Flops)
#1module top_module ( input clk, // Clocks are used in sequential circuits input d, output reg q );// always @(posedge clk) begin q <= d; end // Use a clocked always block // copy d to q at every positive edge o原创 2021-03-28 13:02:26 · 101 阅读 · 0 评论 -
HDLBits 刷题之我的代码(全)—(Circuits-Combinational Logic-Karnaugh Map to Circuits)
#1module top_module( input a, input b, input c, output out ); assign out = a | ((~a) & b) | ((~a) & c);endmodule#2module top_module( input a, input b, input c, input d, output out ); assign out =原创 2021-03-27 14:00:08 · 102 阅读 · 0 评论 -
HDLBits 刷题之我的代码(全)—(Circuits-Combinational Logic-Arithmetic Circuits)
#1module top_module( input a, b, output cout, sum ); assign {cout,sum} = a + b;endmodule#2module top_module( input a, b, cin, output cout, sum ); assign {cout,sum} = a + b + cin;endmodule#3module top_module( input [2原创 2021-03-27 13:55:16 · 90 阅读 · 0 评论 -
HDLBits 刷题之我的代码(全)—(Circuits-Combinational Logic-Multiplexers)
#1module top_module( input a, b, sel, output out ); assign out = sel ? b:a;endmodule#2module top_module( input [99:0] a, b, input sel, output [99:0] out ); assign out = sel ? b:a;endmodule#3module top_module( input [原创 2021-03-27 13:50:16 · 80 阅读 · 0 评论 -
HDLBits 刷题之我的代码(全)—(Circuits-Combinational Logic_Basic Gates)
#1module top_module ( input in, output out); assign out = in;endmodule#2module top_module ( output out); assign out = 1'b0;endmodule#3module top_module ( input in1, input in2, output out); assign out = ~(in1 | in2);e原创 2021-03-27 13:47:20 · 132 阅读 · 0 评论 -
HDLBits 刷题之我的代码(全)—(Verilog Language-More Verilog Features)
#1module top_module ( input [7:0] a, b, c, d, output [7:0] min);// assign min = (a < b) ? ((a < c) ? (a < d ? a : d):(c < d ? c : d)) : ((b < c) ? (b < d ? b : d):(c < d ? c : d)); // assign intermediate_result1 = comp原创 2021-03-27 13:38:04 · 98 阅读 · 0 评论 -
HDLBits 刷题之我的代码(全)—(Verilog Language-Procedures)
#1module top_module( input a, input b, output wire out_assign, output reg out_alwaysblock); assign out_assign = a & b; always @(*) begin out_alwaysblock = a & b; endendmodule#2// synthesis verilog_input_version原创 2021-03-27 13:32:59 · 118 阅读 · 0 评论 -
HDLBits 刷题之我的代码(全)—(Verilog Language-Modules:Hierarchy)
HDLBits 刷题之我的代码(全)—(Verilog Language-Modules:Hierarchy)#1module top_module ( input a, input b, output out ); mod_a u_mod_a( .in1(a), .in2(b), .out(out) );endmodule#2module top_module ( input a, input b,原创 2021-03-27 13:25:37 · 108 阅读 · 0 评论 -
HDLBits 刷题之我的代码(全)—(Verilog Language-Vectors)
HDLBits 刷题之我的代码(全)—(Verilog Language-Vectors)#1module top_module ( input wire [2:0] vec, output wire [2:0] outv, output wire o2, output wire o1, output wire o0 ); // Module body starts after module declaration assign outv = vec;原创 2021-03-27 13:16:30 · 96 阅读 · 0 评论 -
HDLBits 刷题之我的代码(全)—(Verilog Language-Basics)
HDLBits 刷题之我的代码(全)—(Verilog Language-Basics)#1module top_module( input in, output out ); assign out = in;endmodule#2module top_module( input a,b,c, output w,x,y,z ); assign w = a; assign x = b; assign y = b; assign z = c;原创 2021-03-27 13:09:25 · 68 阅读 · 0 评论 -
HDLBits 刷题之我的代码(全)—(Getting started)
HDLBits 刷题之我的代码(全)—(Getting started)#1module top_module( output one );// Insert your code here assign one = 'd1;endmodule#2module top_module( output zero);// Module body starts after semicolon assign zero = 'd0;endmodule...原创 2021-03-27 12:58:20 · 89 阅读 · 0 评论