verilog时钟计数器

题目：
Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second).

reset resets the clock to 12:00 AM. pm is 0 for AM and 1 for PM. hh, mm, and ss are two BCD (Binary-Coded Decimal) digits each for hours (01-12), minutes (00-59), and seconds (00-59). Reset has higher priority than enable, and can occur even when not enabled.

The following timing diagram shows the rollover behaviour from 11:59:59 AM to 12:00:00 PM and the synchronous reset and enable behaviour.
Note that 11:59:59 PM advances to 12:00:00 AM, and 12:59:59 PM advances to 01:00:00 PM. There is no 00:00:00.
代码：

 module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 
    
    reg en1,en2,en3,en4;
    //分和秒的例化
    count1 c1(clk,reset,ena,ss[3:0],en1);
    count2 c2(clk,reset,en1,ss[7:4],en2);
    count1 c3(clk,reset,en2,mm[3:0],en3);
    count2 c4(clk,reset,en3,mm[7:4],en4);
    //时计数
    always@(posedge clk)begin
        if(reset)
            hh<=8'h12;
        else begin
            if(en4)
                if(hh==8'h12)
                    hh<=8'h01;
                    else begin
                if(hh[3:0]==4'd9)
                    hh<=8'h10;
                else
                    hh[3:0]<=hh[3:0]+1;
                    end
        end       
      end
      //pm值
    always@(posedge clk)begin
        if(reset)
            pm<=0;
        else 
            if(en4&hh==8'h11)
               pm<=~pm;
            else;
    end
    endmodule

//例化模块0-9
module count1(
   input clk,
   input reset,
   input in,
    output [4:0]out,
    output en);
    always@(posedge clk)begin
        if(reset)
            out<=0;
        else begin
            if(in)begin
                if(out==4'd9)
                    out<=0;
               else
                   out<=out+1;
            end
            else
               out<=out; 
endmodule
        end
    end
    assign en=out[3]&out[0]&in;
endmodule
//例化模块0-5
module count2(
   input clk,
   input reset,
   input in,
    output [4:0]out,
    output en);
    always@(posedge clk)begin
        if(reset)
            out<=0;
        else begin
            if(in)begin
                if(out==4'd5)
                    out<=0;
               else
                   out<=out+1;
            end
            else
               out<=out; 
        end
    end
    assign en=out[2]&out[0]&in;
endmodule