[UVM]UVM Phases最詳細的介紹

最新推荐文章于 2024-09-28 23:15:50 发布

元直数字电路验证

最新推荐文章于 2024-09-28 23:15:50 发布

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UVM Phases最詳細的介紹

一、The UVM Phases are,

1.1、The run phase is implemented as a task and remaining all are function.

1.2、Q&A

二、 Phases can be grouped into 3 categories,

1. Build Phases

2. Run-time Phases

3. Clean up Phases

二、Phases Description:

三、UVM run phase phases

UVM Phases are a synchronizing mechanism for the environment
Phases are represented by callback methods, A set of predefined phases and corresponding callbacks are provided in uvm_component. The Method can be either a function or task.
Any class deriving from uvm_component may implement any or all of these callbacks, which are executed in a particular order

一、The UVM Phases are,

build
connect
end of elaboration
start of simulation
run
extract
check
report

1.1、The run phase is implemented as a task and remaining all are function.

Note1：run_phase和main_phase或者說run_phase與右邊的12個phase是並行run的，他們之間並沒有包含關係。
Note2：一般地，比較推薦將driver和monitor run在main_phase，而把reference、Scoreboard和Subscriber run在run_phase
Note3：右邊的12個phase是串行執行的，開發中沒必要全部都使用。一般地只會細化到reset_phase、configure_phase、main_phase、shutdown_phase這四個。

1.2、Q&A

Q：为什么要分成小的phase？
Q：这12个小的phase与run_phase之间关系如何？
A：分成小的phase是为了实现更加精细化的控制。如这12个小phase的名字所示，reset，configure，main，shutdown四个phase是核心，这四个phase通常也是模拟了DUT的正常工作方式，在reset_phase对DUT进行复位，初始化等操作，在configure_ phase则进行DUT的配置，DUT的运行主要在main_phase完成，shutdown_phase则是做一些与DUT断电相关的操作。通过细分，对DUT实现更加精确的控制。如，假设要对DUT在运行过程中进行一次reset操作，在没有这些细分的phase之前，这种操作要在scoreboard，reference model等加入一些额外的代码来保证验证平台不会出错。但是有了这些小的phase之后，分别在scoreboard和reference model及其它部分（如driver，monitor等）的reset_phase写好相关代码，之后如果想做一次复位操作，那么只要通过phase的jump，就会自动的跳转回reset_phase。
A：这12个动态运行的phase与run_phase之间有什么关系。从本小节的图中可以看出，这12个动态运行的phase与run_phase之间是并列的关系，这是不是也意味着它们之间的执行也是并列的呢？答案是确定的。对于同一个component来说，如果其同时定义了run_phase和其它12个小的phase，那么其执行大体如下：

fork
  begin
    run_phase();
  end
  
  begin
    pre_reset_phase();
    reset_phase();
    post_reset_phase();
    pre_configure_phase();
    configure_phase();
    post_configure_phase();
    pre_main_phase();
    main_phase();
    post_main_phase();
    pre_shutdown_phase();
    shutdown_phase();
    post_shutdown_phase();
  end

join_none

Note：这段代码只是形象的说明这12个小的phase与run_phase之间的关系，但是有一点要指出的是，这12个小的phase之间并不是这样顺序执行，而是每当一个小的phase执行完成的时候要看看其它component的同名的小phase有没有执行完，等所有的都执行完后，才会进入下一个小的phase，也就是说有一个同步的过程。这段代码中并没有体现出这种同步的过程。

二、 Phases can be grouped into 3 categories,

1. Build Phases

build phase, connect phase and end_of_elobaration phase belongs to this category.Phases in this categorize are executed at the start of the UVM testbench simulation, where the testbench components are constructed, configured and testbench components are connected.All the build phase methods are functions and therefore execute in zero simulation time.

2. Run-time Phases

start of simulation and run phase belongs to run-time phases, the run phase will get executed from the start of simulation to till the end of the simulation.the run phase is time-consuming, where the testcase is running

3. Clean up Phases

extract, check, report and final belong to this category.where the results of the testcase are collected and reported. example: the number of error’s during the simulation is reported.

二、Phases Description:

Phase	Description	Execution Order
build	Used to construct the testbenchcomponents	top-down
connect	Used to connect TLM ports of components	bottom-up
end_of_elaboration	Used to make any final adjustments to the structure, configuration or connectivity of the testbench before simulation starts	bottom-up
start_of_simulation	used for printing testbench topology or configuration information	bottom-up
run	Used for stimulus generation, driving, monitoring, and checking	parallel
extract	Used to retrieve and process information from scoreboards and functional coverage monitors
check	Used to check that the DUT behaved correctly and to identify any errors that may have occurred during the execution of the test bench
report	Used to display the results of the simulation or to write the results to file
final	Used to complete any other outstanding actions that the test bench has not already completed

三、UVM run phase phases

the run phase has different phases, these are,

run	Phase	Description
	pre_reset	the pre_reset phase starts at the same time as the run phase. Its purpose is to take care of any activity that should occur before the reset, such as waiting for a power-good signal to go active
	reset	The reset phase is reserved for DUT or interface specific reset behavior. For example, this phase would be used to generate a reset and to put an interface into its default state
	post_reset	Intended for any activity required immediately the following reset
	pre_configure	pre_configure phase is intended for anything that is required to prepare for the DUT’s configuration process after reset is completed
	configure	configure phase is used to program the DUT and any memories in the testbench so that it is ready for the start of the test case
	post_configure	post_configure phase is used to wait for the effects of configuration to propagate through the DUT, or for it to reach a state where it is ready to start the main test stimulus
	pre_main	pre_main phase is used to ensure that all required components are ready to start generating stimulus
	main	This is where the stimulus specified by the test case is generated and applied to the DUT. It completes when either all stimulus is exhausted or a timeout occurs
	post_main	This phase is used to take care of any finalization of the main phase
	pre_shutdown	This phase is a buffer for any DUT stimulus that needs to take place before the shutdown phase
	shutdown	The shutdown phase is used to ensure that the effects of the stimulus generated during the main phase have propagated through the DUT and that any resultant data has drained away
	post_shutdown	Perform any final activities before exiting the active simulation phases. At the end of the post_shutdown phase, the UVM testbench The execution process starts the cleanup phases