今天把工程移了个地方,结果又报Black Box问题:
[DRC INBB-3] Black Box Instances: Cell 'xillybus_ins/system_i/vivado_system_i/xillyvga_0/inst/xillyvga_core_ins' of type 'xillyvga_core' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
解决办法很简单,手动加一下xillybus_core.ngc和xillyvga_core.ngc,命令如下:
read_edif /文件所在路径/xillybus_core.ngc
read_edif /文件所在路径/xillyvga_core.ngc