Fsm serial

最新推荐文章于 2024-03-29 14:17:11 发布

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最新推荐文章于 2024-03-29 14:17:11 发布

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分类专栏： HDLBits 文章标签： verilog

本文链接：https://blog.csdn.net/hahaha88123/article/details/121236872

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Fsm serial存在的疑问

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module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output done
); 
     enum logic[3:0]{
        stop1=4'b0001,start=4'b0010,data=4'b0100,stop=4'b1000
    } state,next_state;

    logic [3:0] counter = 1'b0;
    always_comb
        begin
            case(state)
                start:begin next_state <=(in)?start:data;end
                data: begin   if(counter==4'd7) begin next_state <= stop; end else next_state<=data; end
                stop: begin  if(in)next_state <= start;else next_state <= stop1;  end
                stop1:begin next_state <=(in)?start:stop1;  end
                default :begin  next_state <= start;end
            endcase
        end
     always_ff@(posedge clk)
        begin
           if(reset)
              state <= start;
           else
              state <= next_state;
         end 
	 always_ff@(posedge clk)
        begin
           if(state==data)
              begin
                if(counter=='d7)
                    counter <= 1'b0;
                else                                 
                    counter <= counter + 1;
              end
           else
              counter <= 1'b0;         //如果不加这个条件就会出现错误
           if(state==stop && in==1'b1)
               done <= 1'b1;
            else
               done <= 1'b0;
          end    
endmodule