Fsm serial(采用计数器的方法)

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已于 2023-02-18 16:07:54 修改

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分类专栏： HDLBits练习文章标签： fpga开发

于 2023-02-18 16:06:37 首次发布

本文链接：https://blog.csdn.net/qq_16379823/article/details/129101371

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module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output done
); 
    reg [3:0] cnt;
    parameter IDLE=0,START=1,STOP=2,WAIT=3;
    reg [1:0] state,next;
    always@(posedge clk)
        if(reset)
            state<=IDLE;
    else 
        state <= next;
    always@(*)begin
        next = 'bx;
        case(state)
            IDLE:next=in?IDLE:START;
            START:next=(cnt<'d8)?START:
                			in?STOP:WAIT;
            WAIT:next = in?IDLE:WAIT;
            STOP:next = in?IDLE:START;
        endcase
    end
    always@(posedge clk)
        if(reset) cnt <= 1'b0;
    else cnt <= (state==START)?(cnt+1'b1):1'b0;
    assign done = (state == STOP);
endmodule