sv数据类型学习一

module tb;
logic [7:0] logic_vec = 8'b1000_0000;
bit [7:0] bit_vec = 8'b10000_0000;
byte signed_vec = 8'b1000_0000;

initial begin
    $display("logic_vec = %d", logic_vec);
    $display("bit_vec = %d", bit_vec);
    $display("signed_vec = %d", signed_vec);
end

byte signed_vec1 = 8'b1000_0000;
bit [8:0] result_vec;
initial begin
    result_vec = signed_vec1;
    $display("@1result_vec = 'h%x", result_vec);
    result_vec = unsigned'(signed_vec1);//静态转化
    $display("@2result_vec = 'h%x", result_vec);
end

logic [3:0] x_vec = 'b111x;
bit [2:0] b_vec; 
initial begin
    $display("@1 x_vec = 'b%b", x_vec);
    b_vec = x_vec;    //四值逻辑的 x z  转化成2值逻辑的值一定是为 0
    $display("@b_vec = 'b%b", b_vec);
end

endmodule

运行结果：

logic_vec = 128
bit_vec =   0
signed_vec =        -128
@1result_vec = 'h180
@2result_vec = 'h080
@1 x_vec = 'b111x
@b_vec = 'b110