公众号:EasyIC
Self Gating 技术
通过插入一个 nand,or,xor 类型的组合逻辑 cell(comparator)如下图 A,comparator 比较寄存器 D 和 Q 的值,结果作为 enable 信号给到 ICG 的 enable,ICG 的 输出连到寄存器的 CLK 上。
其结果是:会降低寄存器的动态功耗,但是 tree 上的 leakage 功耗会变大。
图 A
不同类型的 comparator cell (图 B)
图 B
用于控制 self gating 插入的命令:set_self_gating_objects
使用命令 report_self_gating -gated
查看 gating 效果
参考流程:
shell_is_in_topographysical mode
self gating 不会插入的情况有:
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ILM 内部的寄存器
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已经有 ICG 的寄存器
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已经有 self-gating 的寄存器
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已经在 scan chain 上的寄存器
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total power 没有降低
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插入会引起 timing violation
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dont'touch , false path 等 sdc 引起的原因
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retention 寄存器
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master-slave 寄存器
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registers with non-standard synchronous pin ie:pins other than synchronous set ,reset or load
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low toggle rate
You can use the report_self_gating -ungated
command to identify why self gates are not getting inserted. Note that self gating is effective in a certain range of toggle rates. If toggle rate is too low, self gating does not save power because dynamic power becomes negligible. If toggle rate is too high, the self gates are hardly used and therefore are a waste of area. Self gating is beneficial when toggle rate is neither too high nor too low. To test self gating on a very small design, you might have to try with various values of constraints. The following figure helps you implement self gating in your design and ensure self gates are inserted. If self gates are not inserted after following these steps, open a STAR.You can use the report_self_gating -ungated
command to identify why self gates are not getting inserted. Note that self gating is effective in a certain range of toggle rates. If toggle rate is too low, self gating does not save power because dynamic power becomes negligible. If toggle rate is too high, the self gates are hardly used and therefore are a waste of area. Self gating is beneficial when toggle rate is neither too high nor too low. To test self gating on a very small design, you might have to try with various values of constraints. The following figure helps you implement self gating in your design and ensure self gates are inserted. If self gates are not inserted after following these steps, open a STAR.
Formality 需要 使用如下变量保证插完 self-gating 的设计 LEC 能 PASS
set verification_clock_gate_hold_mode any ;# default is none
(Formality by default will not consider circuitry having clock gates (ICG) equivalent with that has no clock gates)