JTAG（Joint Test Action Group）

0、开篇明义

• JTAG不只是用来给MCU/FPGA等烧写程序。
• JTAG最初用来作为边界扫描测试（Boundary Scan Test），IEEE Standard 1149.1-1990。

1、管脚

1.1、4 wire JTAG

Pin	Description
TCK（Test Clock Input）	Mandatory，TCK provides the clock for the test logic.
TMS（Test Mode Select Input）	Mandatory，The value of the signal present at TMS at the time of a rising edge at TCK determines the next state of the TAP controller, the circuit that controls test operations.
TDI（Test Data Input）	Mandatory，Serial test instructions and data are received by the test logic at TDI.
TDO（Test Data Output）	Mandatory，TDO is the serial output for test instructions and data from the test logic.
TRST（Test Reset Input）	Optional，The optional TRST* input provides for asynchronous initialization, principally at power-up, of the TAP controller, the test mode persistence (TMP) controller, and possibly other test logic. It has a broader effect than simply moving the TAP controller state machine to the Test-Logic-Reset state. TRST* is required when the test logic does not power-up in a known and controlled state, either because of the nature of the underlying technology or because there is no on-chip power-up reset generator.

备注：nTRST之所以是可选的，是因为Reset可以通过TMS的某种pattern来实现。

1.2、2 wire JTAG

Pin	Description
TCK（Test Clock）	Mandatory，
TDI/TDO（Test Data In/Out）	Mandatory，