4位串行进位加法器 与 4位串行借位减法器

4位串行进位加法器：
全加器的算法为：
S = X ^ Y ^ C_in ;
C_out = X*Y + X*C_in + Y*C_in ;
对应的verilog代码为：

module adder_4bits(A, B, C_in, S_out, C_out);
    input [3:0] A;
    input [3:0] B;
    input C_in;
    output [3:0] S_out;
    output C_out;

	 reg [3:0] S_out;
	 reg C_out;
	 reg [1:0] T1, T2, T3, T0;

	 task ADD;

		input A, B, C_in;
		output [1:0] T;

		reg [1:0] T;
		reg S_out, C_out;

		begin
			S_out = A ^ B ^ C_in;
			C_out = (A&B) | (A&C_in) | (B&C_in);

			T = {C_out, S_out};
		end
	 endtask

	always @(A or B or C_in) begin
		 ADD (A[0], B[0], C_in, T0);
		 ADD (A[1], B[1], T0[1], T1);
		 ADD (A[2], B[2], T1[1], T2);
		 ADD (A[3], B[3], T2[1], T3);

		 S_out = {T3[0], T2[0], T1[0], T0[0]};
		 C_out = T3[1];
	end

endmodule

得到的功能仿真图为：

[img]http://dl.iteye.com/upload/attachment/372086/d9d5d5d4-2134-313e-836c-2b21b4998b6d.bmp[/img]

[color=darkred][size=medium]总结：任何n位加法器电路都可以用作减法器，方法是将减数取反，将进位输入和进位输出处理成具有相反有效电平的借位信号。[/size][/color]
4位串行借位减法器的verilog代码如下：

module subtractor_4bits(A, B, C_in, S_out, C_out);
    input [3:0] A;
    input [3:0] B;
    input C_in;
    output [3:0] S_out;
    output C_out;

	 reg [3:0] S_out;
	 reg C_out;
	 reg [1:0] T1, T2, T3, T0;

	 task SUB;

		input A, B, C_in;
		output [1:0] T;

		reg B_n, C_in_n, C_out_n;

		reg [1:0] T;
		reg S_out, C_out;


		begin
			B_n = ~B;
			C_in_n = ~C_in;
			S_out = A ^ B_n ^ C_in_n;
			C_out = (A&B_n) | (A&C_in_n) | (B_n&C_in_n);
			C_out_n = ~C_out;
			T = {C_out_n, S_out};
		end



	 endtask

	always @(A or B or C_in) begin
		 SUB (A[0], B[0], C_in, T0);
		 SUB (A[1], B[1], T0[1], T1);
		 SUB (A[2], B[2], T1[1], T2);
		 SUB (A[3], B[3], T2[1], T3);

		 S_out = {T3[0], T2[0], T1[0], T0[0]};
		 C_out = T3[1];
	end

endmodule

得到的功能仿真图为：

[img]http://dl.iteye.com/upload/attachment/372092/315c2ee3-44b3-37e2-96d1-c967889a7c7a.bmp[/img]
[color=darkred][size=medium]注意：当被减数小于减数是，得到的波形结果是以补码显示为准，这时，应借助C_out值可算出真实的负数值。[/size][/color]