一、概述
利用FPGA来实现流水灯,没有端口限制,只要是用户IO口,都可以使用。本设计是基于FPGA开发板上的晶振时钟分频设计的流水灯。下面是流水灯的两种写法,计数和循环移位。
我所使用的开发板是EGO1开发板,晶振时钟为100MHZ。
二、代码
1、计数写法
module led_water
#(parameter u1s_max = 27'd99_999_999) // 1s计数最大值
(clk,rst,led);
input clk,rst;
output [7:0]led;
reg [7:0]led;
reg [26:0]u1s;
reg [2:0]cnt;
//产生1s延时信号
always @(posedge clk or negedge rst)
begin
if(!rst)
u1s <= 0;
else if(u1s == u1s_max)
u1s <= 0;
else
u1s <= u1s + 1;
end
//利用cnt计数
always @(posedge clk or negedge rst)
begin
if(!rst)
cnt <= 0;
else if((cnt == 7)&&(u1s == u1s_max))
cnt <= 0;
else if(u1s == u1s_max)
cnt <= cnt + 1;
else
cnt <= cnt;
end
//根据cnt计数值来确定LED灯状态
always @(*)
case(cnt)
0:led <= 8'b0000_0001;
1:led <= 8'b0000_0010;
2:led <= 8'b0000_0100;
3:led <= 8'b0000_1000;
4:led <= 8'b0001_0000;
5:led <= 8'b0010_0000;
6:led <= 8'b0100_0000;
7:led <= 8'b1000_0000;
default:led <= 8'b0000_0000;
endcase
endmodule
2、循环移位写法
module led_water
#(parameter u1s_max = 27'd99_999_999)
(clk,rst,led);
input clk,rst;
output [7:0]led;
reg [7:0]led;
reg [26:0]u1s;
//产生1s延时信号
always @(posedge clk or negedge rst)
begin
if(!rst)
u1s <= 0;
else if(u1s == u1s_max)
u1s <= 0;
else
u1s <= u1s + 1;
end
//流水灯循环移位操作
always @(posedge clk or negedge rst)
begin
if(!rst)
led <= 8'b0000_0001;
else if(u1s == u1s_max)
led <= {led[6:0],led[7]};
end
endmodule