fpga 定时器

来源

 

程序设计

   该定时器的程序设计中主要包含CRTL计数模块、SEL2选择模块和DSIP译码器模块三部分的设计。

3．1计数模块

　　CTRL计数模块是该定时器的核心部分。RES为复位端，用来清零，采用异步复位方式；CN用于置位，高电平有效。COUT端将在定时结束时产生高电平。LOW和HIGH为四位BCD码输出端口，可用于显示。当CN有效时，CLK脉冲上升沿到来，计数加1；当CN为低电平时，置位结束，进入计时阶段，每60个时钟周期（相当于一分钟）发出一个脉冲，使输出计数减1，直到计时结束，使COUT位为高电平为止。该模块的源程序:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity ctrl is

  port(cn,res,clk:in std_logic;

        cout:out std_logic;

         low,high:out std_logic_vector(3 downto 0)) ;

end ctrl;

architecture rtl of ctrl  is

signal displow,disphigh:std_logic_vector(3 downto 0);

  begin

  a:process(clk,cn,res)

       variable cnt:integer range 0 to 59;

   begin

     if(res='0')then

        displow<="0000";

         disphigh<="0000";

         cnt:=0;

         cout<='0' ;

   elseif(clk'event and clk='1')then

          if cn='1'then

            if displow<"1001"then

                displow<=displow+'1';

             else displow<="0000";

                 disphigh<=disphigh+'1';

              end if;

            else

                if cnt<59 then

                   cnt:=cnt+1;

                 else

                   cnt:=0;

                 if displow>1 then

                     displow<=displow-'1';

                  elseif displow=1 then

                           displow<="0000";

                          if disphigh=0 then

                                cout<='1';

                           end if;

                   elseif(disphigh>0)then

                         disphigh<=disphigh-'1';

                            displow<="1001";

                     end if;

                   end if;

                  end if;

                 end if;

       end process;

high<=disphigh;

low<=displow;

end rtl;

                  

3．2选择模块

　　二选一选择模块SEL2的主要作用是接收由ctrl输出的四位BCD码，并通过选择信号sel进行选择输出。其源程序如下：

    entity sel2 is

        port(d1,d2:in std_logic_vector(3 downto 0);

              sel:in std_logic;

                q:out std_logic_vector(3 downto 0))

     end sel;

     architecture rtl of sel2 is

      begin

         q<=d1 when sel='1'else

              d2;

      end rtl;

3．3译码器模块

　　译码器模块DISP的作用是对输入四位BCD码进行七段码译码，其输出Q0～Q6分别接数码管的

a～g段，它的操作规程源程序如下：

       entity disp is

         port(d:in std_logic_vector(3 downto 0);

               q:out std_logic_vector(6 downto 0))    

        end disp;

        architecture rtl of disp is

        begin

          process(d)

           begin

               case d is

               when "0000"=>q<="0111111";

               when "0001"=>q<="0000110";

               when "0010"=>q<="1011011";

               when "0011"=>q<="1001111";

               when "0100"=>q<="1100110";

               when "0101"=>q<="1101101";

               when "0110"=>q<="1111101";

               when "0111"=>q<="0000111";

               when "1000"=>q<="1111111";          

               when ohers=>q<="11011111";

               end case;

            end process;

          end rtl;