FPGA定时器的计数设置，是否要减1？（精密计数）

parameter T1US = 5'd20;  //时钟晶振为20MHz

     /*******************************/

    reg [4:0]Count_1US;

     reg is1US;

    always @ ( posedge CLK or negedge RSTn )

        if( !RSTn )

              begin Count_1US <= 5'd0; is1US <= 1'b0; end

          else if( Count_1US == T1US )

              begin Count_1US <= 5'd0; is1US <= 1'b1; end

          else

              begin Count_1US <= Count_1US + 1'b1; is1US = 1'b0; end

仿真结果如下：