verilog语言状态机三段式模板:
//状态机三段式
module divider7(
input sys_clk,
output sys_rst_n,
output reg clk_divider_7
);
//define parameter
parameter S0= 7'b0000001;
parameter S1= 7'b0000010;
parameter S2= 7'b0000100;
parameter S3= 7'b0001000;
parameter S4= 7'b0010000;
parameter S5= 7'b0100100;
parameter S6= 7'b1001000;
//reg define
reg [6:0] curr_state;
reg [6:0] next_state;
//状态机第一段,使用always@()同步时序描述状态转移
always@(posedge sys_clk or negedge sys_rst_n)
begin
if(!sys_rst_n)
curr_state<=S0;
else
curr_state<=next_state;
end
//第二个状态机采用组合逻辑判断状态转移条件
always@(*)
begin
case(curr_state)
S0:next_state=S1;
S1:next_state=S2;
S2:next_state=S3;
S3:next_state=S4;
S4:next_state=S5;
S5:next_state=S6;
S6:next_state=S0;
default:next_state=S0;
endcase
end
//第三段描述状态输出,采用时序电路输出
always@(posedge sys_clk or negedge sys_rst_n)
begin
if(!sys_rst_n)
clk_divider_7<=1'b0;
else if((curr_state==S0)|(curr_state==S1)|(curr_state==S2)|(curr_state==S3))
clk_divider_7<=1'b0;
else if((curr_state==S4)|(curr_state==S5)|(curr_state==S6))
clk_divider_7<=1'b1;
else
;
end
endmodule