FPGA中同步置数、同步清零的计数器

定义输入为data，load，clk，reset；输出为out；则代码为：

module    count(out,data,load,reset,clk);

    input clk,reset,load;
    input [7:0] data;

    output [7:0] out;
    reg [7:0] out;

always    @(posedge clk)           //clk上升沿触发
    begin
        if(!reset)
            out <= 8'h00;           //同步清0，低电平有效
        else if(load)
            out <= data;           //同步预置
        else
            out <= out + 1;        //计数
    end
endmodule

测试文件：

module count_test();

reg clk,reset,load;
reg  [7:0] data;

wire [7:0] out;


count count_inst(.clk(clk),.reset(reset),.data(data),.out(out));


initial
        begin
            clk = 0;
            reset = 0;
            load = 0;
            data = 0;
        end


always  #10 clk = ~clk;

always @(posedge clk)
          begin
              load = 1;
             reset = 1;
          end

always @(posedge clk)
          begin
              load = 0;
          end