FPGA中的任务模块

定义输入为a，b，code；输出为c；则：

module    alutask(a,b,c,code);

    input [1:0] code;
    input [3:0] a,b;

    output reg [4:0] c;

task my_and;
input    [3:0] a,b;
output   [4:0] out;

integer    i;
    begin
        for(i=3;i>0;i=i-1)
            out[i] = a[i] & b[i];   //按位与
    end
endtask

always    @(code or a or b)
    begin
        case(code)
            2'b00: my_and(a,b,c);    //调用任务my_and,需注意端口列表的顺序应与任务定义中的一致，这里的a，b，c分别对应任务定义中的a，b，out
            2'b01: c = a|b;
            2'b10: c = a-b;
            2'b11: c = a+b;
        endcase
    end
endmodule

测试程序为：

`include    "alutask.v"

module    alu_tp;

    reg [3:0] a,b;
    reg [1:0] code;

    wire [4:0] c;

parameter    DELY = 100;

alutask    ADD(code,a,b,c);

initial
    begin
        code = 4'd0; a = 4'b0000; b = 4'b1111;
        #DELY    code = 4'd0; a = 4'b0111; b = 4'b1101;
        #DELY    code = 4'd1; a = 4'b0001; b = 4'b0011;
        #DELY    code = 4'd2; a = 4'b1001; b = 4'b0011;
        #DELY    code = 4'd3; a = 4'b0011; b = 4'b0001;
        #DELY    code = 4'd4; a = 4'b0111; b = 4'b1001;
        #DELY    $finish;
    end

initial    $monitor($time,,,"code=%b a=%b b=%b c=%b",code,a,b,c);
endmodule