FPGA学习日记（12）--流水灯-CSDN博客

本文链接：https://blog.csdn.net/jsomin/article/details/123754181

module water_led
#(
    parameter CNT_MAX = 25'd24_999_999
)
(
    input wire sys_clk      ,
    input wire sys_rst_n    ,
    
    output wire [3:0] led_out
);

reg [24:0] cnt;
reg     cnt_flag;
reg [3:0] led_out_reg;
//计数器
always@(posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0)  
        cnt <= 25'd0;
    else if(cnt == CNT_MAX)
        cnt <= 25'd0;
    else 
        cnt <= cnt + 25'd1;
//标志脉冲
always@(posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0)
        cnt_flag <= 1'b0;
    else if(cnt == CNT_MAX - 25'd1)
        cnt_flag <= 1'b1;
    else
        cnt_flag <= 1'b0;
//输出信号
always@(posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0)
        led_out_reg <= 4'b0001;
    else if((led_out_reg == 4'b1000)&&(cnt_flag == 1'b1))
        led_out_reg <= 4'b0001;
    else  if(cnt_flag == 1'b1)
        led_out_reg <= led_out_reg << 1;
    else 
        led_out_reg <= led_out_reg;

assign led_out = ~led_out_reg;        
endmodule

`timescale 1ns/1ns
module tb_water_led();

reg sys_clk;
reg sys_rst_n;

wire [3:0] led_out;

initial 
    begin
        sys_clk = 1'b1;
        sys_rst_n <= 1'b0;
        #20
        sys_rst_n <= 1'b1;
    end

always #10 sys_clk <= ~sys_clk;
water_led
#(
    .CNT_MAX(25'd24)
)
water_led_inst
(
    .sys_clk    (sys_clk   )  ,
    .sys_rst_n  (sys_rst_n )  ,
   
    .led_out    (led_out   )
);
endmodule