filp 同步复位 异步复位

同步复位

module filp

input wire sys_clk;
input wire sys_rst;
input wire in;
output reg out;

always@(posedge sys_clk)//同步复位
    if(sys_rst == 1'b0)
        out <= 1'b0;
    else(sys_rst == 1'b1)
        out <= in;
endmodule

异步复位

module filp

input wire sys_clk;
input wire sys_rst;
input wire in;
output reg out;

always@(posedge sys_clk or negedge)//同步复位
    if(sys_rst == 1'b0)
        out <= 1'b0;
    else(sys_rst == 1'b1)
        out <= in;
endmodule

tb

`timescale 1ns/1ns
module tb_filp();

reg sys_clk;
reg sys_rst;
reg in;
wire out;

initial 
    begin
        sys_clk <= 1'b1;
        sys_rst <= 1'b0;
        in <= 1'b0;
        #20
        sys_rst <= 1'b1;
        #210
        sys_rst <= 1'b0;
        #40
        sys_rst <= 1'b1;
    end

always #10 sys_clk <= ~sys_clk;
always in <= {$random}%2;

filp filp_inst
(
    .sys_clk(sys_clk),
    .sys_rst(sys_rst),
    .in(in),
    .out(out)
);

endmodule