FPGA学习日记（15）--状态机（投币（一元、五角）出可乐（2.5）找零五角）

finiteyhy

已于 2022-10-14 11:09:05 修改

阅读量477

点赞数

分类专栏： FPGA 文章标签： fpga开发

于 2022-04-02 14:00:19 首次发布

本文链接：https://blog.csdn.net/jsomin/article/details/123918226

版权

FPGA 专栏收录该内容

21 篇文章 2 订阅

订阅专栏

输出两位拼接的

module complex_fsm
(
    input wire sys_clk           ,
    input wire sys_rst_n         ,
    input wire pi_money_half     ,
    input wire pi_money_one      ,
    
    output reg po_cola          ,
    output reg po_money         
);

/* parameter   IDLE = 5'b00001;
parameter   HALF = 5'b00010;
parameter   ONE  = 5'b00100;
parameter   ONE_HALF = 5'b01000;
parameter   TWO  = 5'b10000; */

parameter   IDLE     = 5'b00001,
            HALF     = 5'b00010,    
            ONE      = 5'b00100,
            ONE_HALF = 5'b01000,
            TWO      = 5'b10000;

wire [1:0]  pi_money;
reg  [4:0]  state;

assign pi_money ={pi_money_one,pi_money_half};//位拼接方式为pi_money赋值

always@(posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0)   
        state <= IDLE;
    else case(state)
        IDLE    :if(pi_money == 2'b01)
                        state <= HALF;
                else if(pi_money == 2'b10)
                        state <= ONE;
                else
                        state <= IDLE;
        HALF    :if(pi_money == 2'b01)
                        state <= ONE;
                else if(pi_money == 2'b10)
                        state <= ONE_HALF;
                else
                        state <= HALF;
        
        ONE     :if(pi_money == 2'b01)
                        state <= ONE_HALF;
                else if(pi_money == 2'b10)
                        state <= TWO;
                else
                        state <= ONE;
        ONE_HALF:if(pi_money == 2'b01)
                        state <= TWO;
                else if(pi_money == 2'b10)
                        state <= IDLE;
                else
                        state <= ONE_HALF;
        TWO     :if((pi_money == 2'b01)||(pi_money == 2'b10))
                        state <= IDLE; 
                else
                        state <= TWO;
        default:        state <= IDLE;
    endcase

always@(posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0)   
        po_cola <= 1'b0;
    else if (((state == ONE_HALF)&&(pi_money == 2'b10))
           ||((state == TWO)&&(pi_money == 2'b01))
           ||((state == TWO)&&(pi_money == 2'b10)))
        po_cola <= 1'b1;
    else 
        po_cola <= 1'b0;


always@(posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0)   
        po_money <= 1'b0;
    else if((state == TWO)&&(pi_money == 2'b10))
        po_money <= 1'b1;
    else    
        po_money <= 1'b0;
    
        
        
endmodule

`timescale 1ns/1ns
module tb_complex_fsm();

reg sys_clk;
reg sys_rst_n;
reg pi_money_one;
reg pi_money_half;
reg random_data;

wire po_money;
wire po_cola;


initial 
    begin 
        sys_clk =1'b1;
        sys_rst_n <= 1'b0;
        #20 
        sys_rst_n <= 1'b1;
    end
 
always #10 sys_clk = ~sys_clk;
always@(posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0) 
        random_data <= 1'b0;
    else 
        random_data <= {$random}%2;
        
always@(posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0) 
        pi_money_half <= 1'b0;
    else 
        pi_money_half <= random_data;
        
always@(posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0) 
        pi_money_one <= 1'b0;
    else 
        pi_money_one <= ~random_data;
        
wire [4:0] state = complex_fsm_inst.state; 
wire [1:0] pi_money = complex_fsm_inst.pi_money;
      
initial 
    begin   
        $timeformat(-9,0,"ns",6);
        $monitor("@time %t:pi_money_half = %b,pi_money_one = %b, state = %b,po_cola = %b,po_money = %b",$time,pi_money_half,pi_money_one,state,po_cola,po_money);
    end
    
complex_fsm complex_fsm_inst
(
    . sys_clk        (sys_clk)   ,
    . sys_rst_n      (sys_rst_n )   ,
    . pi_money_half  (pi_money_half)   ,
    . pi_money_one   (pi_money_one)   ,
    
    . po_cola        (po_cola )  ,
    . po_money       (po_money )  
);
endmodule

输出的两位没拼接在一个两位信号里的

module complex_state
(
    input   wire    sys_clk,
    input   wire    sys_rst_n,
    input   wire    pi_money_half,
    input   wire    pi_money_one,
    output  reg     po_cola,
    output  reg     po_money
);

parameter IDLE = 5'b00001;
parameter HALF = 5'b00010;
parameter ONE  = 5'b00100;
parameter ONE_HALF = 5'b01000;
parameter TWO  = 5'b10000;
reg [4:0] state;

always@(posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0)
        state <= IDLE;
    else case(state)
        IDLE:if(pi_money_half == 1'b1&&pi_money_one == 1'b0)
                state <= HALF;
             else if(pi_money_one == 1'b1&&pi_money_half == 1'b0)
                state <= ONE;
             else
                state <= IDLE;
        HALF:if(pi_money_half == 1'b1&&pi_money_one == 1'b0)
                state <= ONE;
             else if(pi_money_one == 1'b1&&pi_money_half == 1'b0)
                state <= ONE_HALF;
             else
                state <= HALF;
        ONE:if(pi_money_half == 1'b1&&pi_money_one == 1'b0)
                state <= ONE_HALF;
            else if(pi_money_one == 1'b1&&pi_money_half == 1'b0)
                state <= TWO;
            else
                state <= ONE;
        ONE_HALF:if(pi_money_half == 1'b1&&pi_money_one == 1'b0)
                    state <= TWO;
                 else if(pi_money_one == 1'b1&&pi_money_half == 1'b0)
                    state <= IDLE;  //2.5 
                 else
                    state <= ONE_HALF;
        TWO:if(pi_money_half == 1'b1&&pi_money_one == 1'b0)
                state <= IDLE;
            else if(pi_money_one == 1'b1&&pi_money_half == 1'b0)
                state <= IDLE;
            else
                state <= TWO;            
        default:state <= IDLE;
    endcase
    
always@(posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0)
        begin
            po_cola <= 1'b0;
            po_money <= 1'b0;
        end
    else if((state == ONE_HALF && pi_money_one==1'b1 )||(state == TWO && pi_money_half==1'b1))
        begin
            po_cola <= 1'b1;
            po_money <= 1'b0;
        end
    else if(state == TWO && pi_money_one == 1'b1 )
        begin
            po_cola <= 1'b1;
            po_money <= 1'b1;
        end
    else
        begin
            po_cola <= 1'b0;
            po_money <= 1'b0; 
        end   
        
endmodule

`timescale 1ns/1ns
module tb_complex_state();

reg    sys_clk;
reg    sys_rst_n;
reg    pi_money_half;
reg    pi_money_one;
wire    po_cola;
wire    po_money;
reg     ramdon_data;
initial
    begin
        sys_clk <= 1'b1;
        sys_rst_n <=1'b0;
        #10
        sys_rst_n <= 1'b1;
    end


always #10 sys_clk = ~sys_clk;

//always #10 pi_money_half = {$random} % 2;
//always #10 pi_money_one = {$random} % 2;

always@(posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0)
        ramdon_data <= 1'b0;
    else
        ramdon_data <= {$random}%2;

always@(posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0)
        pi_money_half <= 1'b0;
    else
        pi_money_half <= ramdon_data;
        
always@(posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0)
        pi_money_one <= 1'b0;
    else
        pi_money_one <= ~ramdon_data;        
        
        
wire [4:0] state = complex_state_inst.state;


complex_state complex_state_inst
(
    .sys_clk        (sys_clk        ),
    .sys_rst_n      (sys_rst_n      ),
    .pi_money_half  (pi_money_half  ),
    .pi_money_one   (pi_money_one   ),
    .po_cola        (po_cola        ),
    .po_money       (po_money       )
);

endmodule